intel/fs: Assert fs_reg::nr is always zero for ATTR registers in geometry stages.

Instead of treating fs_reg::nr as an offset for ATTR registers simply
consider different indices as denoting disjoint spaces that can never
be accessed simultaneously by a single region.  From now on geometry
stages will just use ATTR #0 for everything and select specific
attributes via offset() with the native dispatch width of the program,
which should work on current platforms as well as on Xe2+.  See
"intel/fs: Map all GS input attributes to ATTR register number 0." for
the rationale.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>

src/intel/compiler/brw_fs.cpp

@@ -1771,9 +1771,9 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst)
 {
    for (int i = 0; i < inst->sources; i++) {
       if (inst->src[i].file == ATTR) {
+         assert(inst->src[i].nr == 0);
          int grf = payload().num_regs +
                    prog_data->curb_read_length +
-                   inst->src[i].nr +
                    inst->src[i].offset / REG_SIZE;
 
          /* As explained at brw_reg_from_fs_reg, From the Haswell PRM: