anv: ensure tile flush before streamout writes

Streamout is not L3 coherent so previous writes to the same address
might be pending and overwrite the SO writes later when they get
flushed from L3, even though the SO write happened later in the batch.

v2: Use the right flag (not COUNTER)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6680
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17503>

src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt

@@ -1,2 +0,0 @@
-# 6205
-KHR-GL46.tessellation_shader.single.xfb_captures_data_from_correct_stage,Fail

src/intel/vulkan/anv_private.h

@@ -2567,6 +2567,14 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
           */
          pipe_bits |= ANV_PIPE_FLUSH_BITS;
          break;
+      case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
+         /* We're transitioning a buffer to be written by the streamout fixed
+          * function. This one is apparently not L3 coherent, so we need a
+          * tile cache flush to make sure any previous write is not going to
+          * create WaW hazards.
+          */
+         pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
+         break;
       default:
          break; /* Nothing to do */
       }