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r600c: fix some opcodes on evergreen

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There were a few places where we were using the wrong opcodes
on evergreen.  arl still needs to be fixed on evergreen; see
r600g for reference.

NOTE: This is a candidate for the 7.9 branch.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
This commit is contained in:
Alex Deucher
2010-12-01 13:22:00 -05:00
parent e6d798948e
commit 2ca9256911
1 changed files with 56 additions and 8 deletions
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src/mesa/drivers/dri/r600/r700_assembler.c
+56 -8
View File
@@ -3334,7 +3334,14 @@ GLboolean assemble_CMP(r700_AssemblerBase *pAsm)
return GL_FALSE;
}
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_CNDGE;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE;
}
pAsm->D.dst.op3 = 1;
tmp = (-1);
@@ -3416,8 +3423,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode)
checkop1(pAsm);
tmp = gethelpr(pAsm);
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
}
pAsm->D.dst.op3 = 1;
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -3457,7 +3470,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode)
{
return GL_FALSE;
}
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
}
pAsm->D.dst.op3 = 1;
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -4742,7 +4762,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm)
tmp = gethelpr(pAsm);
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
}
pAsm->D.dst.op3 = 1;
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -4782,7 +4809,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm)
{
return GL_FALSE;
}
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
}
pAsm->D.dst.op3 = 1;
setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -5010,7 +5044,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm)
GLuint tmp = gethelpr(pAsm);
/* tmp = (src > 0 ? 1 : src) */
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
}
pAsm->D.dst.op3 = 1;
pAsm->D.dst.rtype = DST_REG_TEMPORARY;
pAsm->D.dst.reg = tmp;
@@ -5033,7 +5074,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm)
}
/* dst = (-tmp > 0 ? -1 : tmp) */
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
if(8 == pAsm->unAsic)
{
pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
}
else
{
pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
}
pAsm->D.dst.op3 = 1;
if( GL_FALSE == assemble_dst(pAsm) )