radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.

The first arg to OUT_BATCH_RELOC is ignored, we actually wanted these
in the third arg.  They're always 0 so far, so it didn't matter.

v2: Reword commit message that I don't end up using the tile bits, but
    keep the commit as a cleanup anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)

src/mesa/drivers/dri/r200/r200_state_init.c

@@ -581,11 +581,11 @@ static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom)
    if (dwords > atom->cmd_size) {
      OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
      if (t->mt && !t->image_override) {
-        OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+        OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, t->tile_bits,
 		  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
       } else {
 	if (t->bo)
-            OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+            OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits,
                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
       }
    }

src/mesa/drivers/dri/radeon/radeon_state_init.c

@@ -488,12 +488,13 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 	    OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
 			RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
         } else {
-           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
+           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo,
+                           get_base_teximage_offset(t) | t->tile_bits,
 		     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
         }
       } else {
 	if (t->bo)
-            OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+            OUT_BATCH_RELOC(t->tile_bits, t->bo, t->tile_bits,
                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
       }
    }