AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

genxml: Add missing INSTDONE_1 bits on Gen7.5+.

Browse Source 
This will make aubinator_error_decode decode them properly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Kenneth Graunke
2018-01-07 22:29:34 -08:00
parent 8eadc2fb8f
commit 28c2d0d80b
4 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/genxml/gen10.xml
+2
View File
@@ -3637,6 +3637,8 @@
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="GAFM Done" start="18" end="18" type="bool"/>
<field name="GAM Done" start="19" end="19" type="bool"/>
<field name="RS Done" start="20" end="20" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
<field name="SDE Done" start="22" end="22" type="bool"/>
<field name="RCCFBC CS Done" start="23" end="23" type="bool"/>
</register>
src/intel/genxml/gen75.xml
+2
View File
@@ -3046,6 +3046,8 @@
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="GAFM Done" start="18" end="18" type="bool"/>
<field name="GAM Done" start="19" end="19" type="bool"/>
<field name="RS Done" start="20" end="20" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
<field name="SDE Done" start="22" end="22" type="bool"/>
<field name="RCCFBC CS Done" start="23" end="23" type="bool"/>
</register>
src/intel/genxml/gen8.xml
+2
View File
@@ -3300,6 +3300,8 @@
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="GAFM Done" start="18" end="18" type="bool"/>
<field name="GAM Done" start="19" end="19" type="bool"/>
<field name="RS Done" start="20" end="20" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
<field name="SDE Done" start="22" end="22" type="bool"/>
<field name="RCCFBC CS Done" start="23" end="23" type="bool"/>
</register>
src/intel/genxml/gen9.xml
+2
View File
@@ -3583,6 +3583,8 @@
<field name="TSG Done" start="17" end="17" type="bool"/>
<field name="GAFM Done" start="18" end="18" type="bool"/>
<field name="GAM Done" start="19" end="19" type="bool"/>
<field name="RS Done" start="20" end="20" type="bool"/>
<field name="CS Done" start="21" end="21" type="bool"/>
<field name="SDE Done" start="22" end="22" type="bool"/>
<field name="RCCFBC CS Done" start="23" end="23" type="bool"/>
</register>