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i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD

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gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen
2014-05-28 09:05:37 -07:00
parent 7e856d0b18
commit 27f5fa7a37
7 changed files with 35 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/intel_fbo.c
+2 -1
View File
@@ -980,7 +980,8 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
width, height, depth,
true,
irb->mt->num_samples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
if (brw_is_hiz_depth_format(brw, new_mt->format)) {
intel_miptree_alloc_hiz(brw, new_mt);
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+21 -10
View File
@@ -232,7 +232,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
GLuint num_samples)
GLuint num_samples,
bool force_all_slices_at_each_lod)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
@@ -388,7 +389,8 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_depth0,
true,
num_samples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
@@ -406,6 +408,9 @@ intel_miptree_create_layout(struct brw_context *brw,
}
}
if (force_all_slices_at_each_lod)
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
brw_miptree_layout(brw, mt);
return mt;
@@ -560,7 +565,8 @@ intel_miptree_create(struct brw_context *brw,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
enum intel_miptree_tiling_mode requested_tiling)
enum intel_miptree_tiling_mode requested_tiling,
bool force_all_slices_at_each_lod)
{
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
@@ -574,7 +580,8 @@ intel_miptree_create(struct brw_context *brw,
mt = intel_miptree_create_layout(brw, target, format,
first_level, last_level, width0,
height0, depth0,
false, num_samples);
false, num_samples,
force_all_slices_at_each_lod);
/*
* pitch == 0 || height == 0 indicates the null texture
*/
@@ -685,7 +692,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt = intel_miptree_create_layout(brw, GL_TEXTURE_2D, format,
0, 0,
width, height, 1,
true, 0 /* num_samples */);
true, 0, false);
if (!mt) {
free(mt);
return mt;
@@ -794,7 +801,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
mt = intel_miptree_create(brw, target, format, 0, 0,
width, height, depth, true, num_samples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY, false);
if (!mt)
goto fail;
@@ -1295,7 +1302,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
mt->logical_depth0,
true,
0 /* num_samples */,
INTEL_MIPTREE_TILING_Y);
INTEL_MIPTREE_TILING_Y,
false);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
@@ -1352,7 +1360,8 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
mt->logical_depth0,
true,
0 /* num_samples */,
INTEL_MIPTREE_TILING_Y);
INTEL_MIPTREE_TILING_Y,
false);
return mt->mcs_mt;
}
@@ -1408,7 +1417,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
mt->logical_depth0,
true,
mt->num_samples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
if (!mt->hiz_mt)
return false;
@@ -1785,7 +1795,8 @@ intel_miptree_map_blit(struct brw_context *brw,
0, 0,
map->w, map->h, 1,
false, 0,
INTEL_MIPTREE_TILING_NONE);
INTEL_MIPTREE_TILING_NONE,
false);
if (!map->mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+4 -2
View File
@@ -503,7 +503,8 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
enum intel_miptree_tiling_mode);
enum intel_miptree_tiling_mode,
bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
@@ -515,7 +516,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
GLuint num_samples);
GLuint num_samples,
bool force_all_slices_at_each_lod);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
src/mesa/drivers/dri/i965/intel_tex.c
+2 -1
View File
@@ -145,7 +145,8 @@ intel_alloc_texture_storage(struct gl_context *ctx,
width, height, depth,
false, /* expect_accelerated */
num_samples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
if (intel_texobj->mt == NULL) {
return false;
src/mesa/drivers/dri/i965/intel_tex_image.c
+2 -1
View File
@@ -81,7 +81,8 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
depth,
expect_accelerated_upload,
intelImage->base.Base.NumSamples,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
}
/* XXX: Do this for TexSubImage also:
src/mesa/drivers/dri/i965/intel_tex_subimage.c
+2 -1
View File
@@ -133,7 +133,8 @@ intel_blit_texsubimage(struct gl_context * ctx,
intel_miptree_create(brw, GL_TEXTURE_2D, texImage->TexFormat,
0, 0,
width, height, 1,
false, 0, INTEL_MIPTREE_TILING_NONE);
false, 0, INTEL_MIPTREE_TILING_NONE,
false);
if (!temp_mt)
goto err;
src/mesa/drivers/dri/i965/intel_tex_validate.c
+2 -1
View File
@@ -137,7 +137,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
depth,
true,
0 /* num_samples */,
INTEL_MIPTREE_TILING_ANY);
INTEL_MIPTREE_TILING_ANY,
false);
if (!intelObj->mt)
return false;
}