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@@ -216,18 +216,18 @@ static void transform_CEIL(struct radeon_compiler* c,
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rc_remove_instruction(inst);
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}
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static void transform_DP3(struct radeon_compiler* c,
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static void transform_DP2(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_src_register src0 = inst->U.I.SrcReg[0];
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struct rc_src_register src1 = inst->U.I.SrcReg[1];
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src0.Negate &= ~RC_MASK_W;
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src0.Swizzle &= ~(7 << (3 * 3));
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src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
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src1.Negate &= ~RC_MASK_W;
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src1.Swizzle &= ~(7 << (3 * 3));
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src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
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emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
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src0.Negate &= ~(RC_MASK_Z | RC_MASK_W);
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src0.Swizzle &= ~(63 << (3 * 2));
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src0.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
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src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
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src1.Swizzle &= ~(63 << (3 * 2));
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src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
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emit2(c, inst->Prev, RC_OPCODE_DP3, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
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rc_remove_instruction(inst);
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}
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@@ -553,6 +553,7 @@ int radeonTransformALU(
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switch(inst->U.I.Opcode) {
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case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
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case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
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case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
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case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
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case RC_OPCODE_DST: transform_DST(c, inst); return 1;
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case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
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@@ -615,6 +616,29 @@ static void transform_r300_vertex_CMP(struct radeon_compiler* c,
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rc_remove_instruction(inst);
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}
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static void transform_r300_vertex_DP2(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_instruction *next_inst = inst->Next;
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transform_DP2(c, inst);
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next_inst->Prev->U.I.Opcode = RC_OPCODE_DP4;
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}
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static void transform_r300_vertex_DP3(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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struct rc_src_register src0 = inst->U.I.SrcReg[0];
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struct rc_src_register src1 = inst->U.I.SrcReg[1];
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src0.Negate &= ~RC_MASK_W;
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src0.Swizzle &= ~(7 << (3 * 3));
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src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
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src1.Negate &= ~RC_MASK_W;
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src1.Swizzle &= ~(7 << (3 * 3));
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src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
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emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
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rc_remove_instruction(inst);
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}
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static void transform_r300_vertex_fix_LIT(struct radeon_compiler* c,
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struct rc_instruction* inst)
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{
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@@ -758,7 +782,8 @@ int r300_transform_vertex_alu(
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case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
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case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
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case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
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case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
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case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
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case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
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case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
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case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
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case RC_OPCODE_LIT: transform_r300_vertex_fix_LIT(c, inst); return 1;
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