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ac/surface: add gfx11 support to modifiers tests

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Marek Olšák
2021-05-06 20:41:47 -04:00
committed by Marge Bot
parent 3e85a0c90b
commit 273674dde1
3 changed files with 86 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_surface_meta_address_test.c
+64 -25
View File
@@ -318,8 +318,24 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf
{
unsigned total = 0;
unsigned fails = 0;
unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_R_X;
unsigned last_size, max_samples, min_bpp, max_bpp;
unsigned swizzle_modes[2], num_swizzle_modes = 0;
switch (info->chip_class) {
case GFX9:
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_S_X;
break;
case GFX10:
case GFX10_3:
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X;
break;
case GFX11:
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X;
swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_R_X;
break;
default:
unreachable("unhandled gfx version");
}
if (full) {
last_size = 6*6 - 1;
@@ -347,25 +363,27 @@ static void run_dcc_address_test(const char *name, const struct radeon_info *inf
unsigned local_fails = 0;
unsigned local_total = 0;
for (unsigned bpp = min_bpp; bpp <= max_bpp; bpp *= 2) {
/* addrlib can do DccAddrFromCoord with MSAA images only on gfx9 */
for (unsigned samples = 1; samples <= (info->chip_class == GFX9 ? max_samples : 1); samples *= 2) {
for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) {
for (int pipe_aligned = true; pipe_aligned >= (samples > 1 ? true : false); pipe_aligned--) {
for (unsigned mrt_index = 0; mrt_index < 2; mrt_index++) {
unsigned depth = 2;
char test[256];
for (unsigned swizzle_mode = 0; swizzle_mode < num_swizzle_modes; swizzle_mode++) {
for (unsigned bpp = min_bpp; bpp <= max_bpp; bpp *= 2) {
/* addrlib can do DccAddrFromCoord with MSAA images only on gfx9 */
for (unsigned samples = 1; samples <= (info->chip_class == GFX9 ? max_samples : 1); samples *= 2) {
for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) {
for (int pipe_aligned = true; pipe_aligned >= (samples > 1 ? true : false); pipe_aligned--) {
for (unsigned mrt_index = 0; mrt_index < 2; mrt_index++) {
unsigned depth = 2;
char test[256];
snprintf(test, sizeof(test), "%ux%ux%u %ubpp %u samples rb:%u pipe:%u",
width, height, depth, bpp, samples, rb_aligned, pipe_aligned);
snprintf(test, sizeof(test), "%ux%ux%u %ubpp %u samples rb:%u pipe:%u",
width, height, depth, bpp, samples, rb_aligned, pipe_aligned);
if (one_dcc_address_test(name, test, addrlib, info, width, height, depth, samples,
bpp, swizzle_mode, pipe_aligned, rb_aligned, mrt_index,
0, 0, 0, 0)) {
} else {
local_fails++;
if (one_dcc_address_test(name, test, addrlib, info, width, height, depth, samples,
bpp, swizzle_modes[swizzle_mode], pipe_aligned,
rb_aligned, mrt_index, 0, 0, 0, 0)) {
} else {
local_fails++;
}
local_total++;
}
local_total++;
}
}
}
@@ -480,7 +498,22 @@ static void run_htile_address_test(const char *name, const struct radeon_info *i
{
unsigned total = 0;
unsigned fails = 0;
unsigned first_size = 0, last_size = 6*6 - 1, max_bpp = 32;
unsigned first_size = 0, last_size = 6*6 - 1;
unsigned swizzle_modes[2], num_swizzle_modes = 0;
switch (info->chip_class) {
case GFX9:
case GFX10:
case GFX10_3:
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_Z_X;
break;
case GFX11:
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_Z_X;
swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_Z_X;
break;
default:
unreachable("unhandled gfx version");
}
/* The test coverage is reduced for Gitlab CI because it timeouts. */
if (!full) {
@@ -497,14 +530,16 @@ static void run_htile_address_test(const char *name, const struct radeon_info *i
struct ac_addrlib *ac_addrlib = ac_addrlib_create(info, NULL);
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
for (unsigned depth = 1; depth <= 2; depth *= 2) {
for (unsigned bpp = 16; bpp <= max_bpp; bpp *= 2) {
if (one_htile_address_test(name, name, addrlib, info, width, height, depth,
bpp, ADDR_SW_64KB_Z_X, 0, 0, 0)) {
} else {
p_atomic_inc(&fails);
for (unsigned swizzle_mode = 0; swizzle_mode < num_swizzle_modes; swizzle_mode++) {
for (unsigned depth = 1; depth <= 2; depth *= 2) {
for (unsigned bpp = 16; bpp <= 32; bpp *= 2) {
if (one_htile_address_test(name, name, addrlib, info, width, height, depth,
bpp, swizzle_modes[swizzle_mode], 0, 0, 0)) {
} else {
p_atomic_inc(&fails);
}
p_atomic_inc(&total);
}
p_atomic_inc(&total);
}
}
@@ -640,6 +675,10 @@ static void run_cmask_address_test(const char *name, const struct radeon_info *i
unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X;
unsigned first_size = 0, last_size = 6*6 - 1, max_bpp = 32;
/* GFX11 doesn't have CMASK. */
if (info->chip_class >= GFX11)
return;
/* The test coverage is reduced for Gitlab CI because it timeouts. */
if (!full) {
first_size = last_size = 0;
src/amd/common/ac_surface_modifier_test.c
+5 -3
View File
@@ -258,12 +258,14 @@ static void test_modifier(const struct radeon_info *info,
assert(surf.cmask_offset == 0);
assert(surf.fmask_offset == 0);
unsigned block_size_bits = surf.u.gfx9.swizzle_mode >= ADDR_SW_256KB_Z_X ? 18 : 16;
uint64_t surf_size;
unsigned aligned_pitch, aligned_height;
if (modifier != DRM_FORMAT_MOD_LINEAR) {
surf_size = block_count(dims[i][0], dims[i][1],
elem_bits, 16, &aligned_pitch,
&aligned_height) << 16;
elem_bits, block_size_bits, &aligned_pitch,
&aligned_height) << block_size_bits;
} else {
aligned_pitch = align(dims[i][0], 256 / util_format_get_blocksize(format));
aligned_height = dims[i][1];
@@ -296,7 +298,7 @@ static void test_modifier(const struct radeon_info *info,
unsigned block_bits;
if (info->chip_class >= GFX10) {
unsigned num_pipes = G_0098F8_NUM_PIPES(info->gb_addr_config);
if (info->chip_class == GFX10_3 &&
if (info->chip_class >= GFX10_3 &&
G_0098F8_NUM_PKRS(info->gb_addr_config) == num_pipes && num_pipes > 1)
++num_pipes;
block_bits = 16 +
src/amd/common/ac_surface_test_common.h
+17
View File
@@ -137,6 +137,22 @@ static void init_gfx103(struct radeon_info *info)
info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
}
static void init_gfx11(struct radeon_info *info)
{
info->family = CHIP_UNKNOWN;
info->chip_class = GFX11;
info->family_id = 0x00;
info->chip_external_rev = 0x01;
info->use_display_dcc_unaligned = false;
info->use_display_dcc_with_retile_blit = true;
info->has_graphics = true;
info->tcc_cache_line_size = 128;
info->has_rbplus = true;
info->rbplus_allowed = true;
info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
}
struct testcase {
const char *name;
gpu_init_func init;
@@ -190,6 +206,7 @@ static struct radeon_info get_radeon_info(struct testcase *testcase)
break;
case GFX10:
case GFX10_3:
case GFX11:
info.gb_addr_config = (info.gb_addr_config &
C_0098F8_NUM_PIPES &
C_0098F8_NUM_PKRS) |