intel/aux_map: Add and use INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN

Introduce a macro so that drivers don't need to rely on the isl_surf
struct to determine the size of the CCS buffer on gfx12.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28942>

src/gallium/drivers/iris/iris_resource.c

@@ -1099,7 +1099,8 @@ iris_resource_create_for_image(struct pipe_screen *pscreen,
    if (res->aux.extra_aux.surf.size_B > 0) {
       res->aux.extra_aux.offset =
          (uint32_t)align64(bo_size, INTEL_AUX_MAP_META_ALIGNMENT_B);
-      bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
+      bo_size = res->aux.extra_aux.offset +
+                res->surf.size_B / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
    }
 
    /* Allocate space for the indirect clear color.
@@ -1323,16 +1324,19 @@ iris_resource_from_handle(struct pipe_screen *pscreen,
             /* Fill out some aux surface fields. */
             assert(isl_drm_modifier_has_aux(whandle->modifier));
             assert(!devinfo->has_flat_ccs);
-            assert(plane_res->bo->size >= plane_res->offset +
-                   main_res->aux.surf.size_B);
 
             if (devinfo->has_aux_map) {
                assert(plane_res->surf.row_pitch_B ==
                       main_res->surf.row_pitch_B /
                       INTEL_AUX_MAP_MAIN_PITCH_SCALEDOWN);
+               assert(plane_res->bo->size >= plane_res->offset +
+                      main_res->surf.size_B /
+                      INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN);
             } else {
                assert(plane_res->surf.row_pitch_B ==
                       main_res->aux.surf.row_pitch_B);
+               assert(plane_res->bo->size >= plane_res->offset +
+                      main_res->aux.surf.size_B);
             }
 
             iris_bo_reference(plane_res->bo);

src/intel/common/intel_aux_map.c

@@ -144,10 +144,6 @@ struct aux_format_info {
     * Granularity of main surface in compression. It must be power of 2.
     */
    uint64_t main_page_size;
-   /**
-    * The ratio of main surface to an AUX entry.
-    */
-   uint64_t main_to_aux_ratio;
    /**
     * Page size of level 1 page table. It must be power of 2.
     */
@@ -165,14 +161,12 @@ struct aux_format_info {
 static const struct aux_format_info aux_formats[] = {
    [INTEL_AUX_MAP_GFX12_64KB] = {
       .main_page_size = 64 * 1024,
-      .main_to_aux_ratio = 256,
       .l1_page_size = 8 * 1024,
       .l1_index_mask = 0xff,
       .l1_index_offset = 16,
    },
    [INTEL_AUX_MAP_GFX125_1MB] = {
       .main_page_size = 1024 * 1024,
-      .main_to_aux_ratio = 256,
       .l1_page_size = 2 * 1024,
       .l1_index_mask = 0xf,
       .l1_index_offset = 20,
@@ -225,7 +219,7 @@ get_page_mask(const uint64_t page_size)
 static inline uint64_t
 get_meta_page_size(const struct aux_format_info *info)
 {
-   return info->main_page_size / info->main_to_aux_ratio;
+   return info->main_page_size / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
 }
 
 static inline uint64_t
@@ -241,17 +235,11 @@ intel_aux_get_meta_address_mask(struct intel_aux_map_context *ctx)
    return (~get_page_mask(get_meta_page_size(ctx->format))) & VALID_ADDRESS_MASK;
 }
 
-uint64_t
-intel_aux_get_main_to_aux_ratio(struct intel_aux_map_context *ctx)
-{
-   return ctx->format->main_to_aux_ratio;
-}
-
 uint64_t
 intel_aux_main_to_aux_offset(struct intel_aux_map_context *ctx,
                              uint64_t main_offset)
 {
-   return main_offset / ctx->format->main_to_aux_ratio;
+   return main_offset / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
 }
 
 static const struct aux_format_info *

src/intel/common/intel_aux_map.h

@@ -55,6 +55,19 @@ struct intel_device_info;
  */
 #define INTEL_AUX_MAP_MAIN_PITCH_SCALEDOWN (512 / 64)
 
+/**
+ * The ratio between the granularity of main surface and AUX data.
+ *
+ * The value is from Bspec 47709, MCS/CCS Buffers for Render Target(s):
+ *
+ *    "CCS is a linear buffer created for storing meta-data (AUX data) for
+ *    lossless compression. This buffer related information is mentioned in
+ *    Render Surface State. CCS buffer's size is based on the padded main
+ *    surface (after following Halign and Valign requirements mentioned in the
+ *    Render Surface State). CCS_Buffer_Size = Padded_Main_Surface_Size/256"
+ */
+#define INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN 256
+
 /**
  * The alignment at which the AUX data virtual addresses should start.
  *
@@ -98,12 +111,6 @@ intel_aux_map_get_num_buffers(struct intel_aux_map_context *ctx);
 uint64_t
 intel_aux_get_meta_address_mask(struct intel_aux_map_context *ctx);
 
-/**
- * Returns the ratio between the granularity of main surface and AUX data
- */
-uint64_t
-intel_aux_get_main_to_aux_ratio(struct intel_aux_map_context *ctx);
-
 /**
  * Takes a relative offset in the main surface and returns a relative offset
  * in the aux surface that maps to the main offset.

src/intel/vulkan/anv_allocator.c

@@ -1597,7 +1597,7 @@ anv_device_alloc_bo(struct anv_device *device,
    const uint64_t ccs_offset = size;
    if (alloc_flags & ANV_BO_ALLOC_AUX_CCS) {
       assert(device->info->has_aux_map);
-      size += DIV_ROUND_UP(size, intel_aux_get_main_to_aux_ratio(device->aux_map_ctx));
+      size += size / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
       size = align64(size, 4096);
    }
 

src/intel/vulkan/anv_image.c

@@ -704,11 +704,9 @@ add_compression_control_buffer(struct anv_device *device,
 {
    assert(device->info->has_aux_map);
 
-   uint64_t ratio = intel_aux_get_main_to_aux_ratio(device->aux_map_ctx);
-   assert(image->planes[plane].primary_surface.isl.size_B % ratio == 0);
-   uint64_t size = image->planes[plane].primary_surface.isl.size_B / ratio;
-
-   return image_binding_grow(device, image, binding, offset, size,
+   return image_binding_grow(device, image, binding, offset,
+                             image->planes[plane].primary_surface.isl.size_B /
+                             INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN,
                              INTEL_AUX_MAP_META_ALIGNMENT_B,
                              &image->planes[plane].compr_ctrl_memory_range);
 }