radeonsi: emit PS exports last
This effectively removes s_waitcnt instructions after FP16 exports.
Before:
v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300
v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702
exp 15, 0, 1, 0, 0, v0, v1, v0, v0 ; F800040F 00000100
s_waitcnt expcnt(0) ; BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v4, v5 ; 5E000B04
v_cvt_pkrtz_f16_f32_e32 v1, v6, v7 ; 5E020F06
exp 15, 1, 1, 0, 0, v0, v1, v0, v0 ; F800041F 00000100
s_waitcnt expcnt(0) ; BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v8, v9 ; 5E001308
v_cvt_pkrtz_f16_f32_e32 v1, v10, v11 ; 5E02170A
exp 15, 2, 1, 0, 0, v0, v1, v0, v0 ; F800042F 00000100
s_waitcnt expcnt(0) ; BF8C0F0F
v_cvt_pkrtz_f16_f32_e32 v0, v12, v13 ; 5E001B0C
v_cvt_pkrtz_f16_f32_e32 v1, v14, v15 ; 5E021F0E
exp 15, 3, 1, 1, 1, v0, v1, v0, v0 ; F8001C3F 00000100
s_endpgm ; BF810000
After:
v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300
v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702
v_cvt_pkrtz_f16_f32_e32 v2, v4, v5 ; 5E040B04
v_cvt_pkrtz_f16_f32_e32 v3, v6, v7 ; 5E060F06
exp 15, 0, 1, 0, 0, v0, v1, v0, v0 ; F800040F 00000100
v_cvt_pkrtz_f16_f32_e32 v4, v8, v9 ; 5E081308
v_cvt_pkrtz_f16_f32_e32 v5, v10, v11 ; 5E0A170A
exp 15, 1, 1, 0, 0, v2, v3, v0, v0 ; F800041F 00000302
v_cvt_pkrtz_f16_f32_e32 v6, v12, v13 ; 5E0C1B0C
v_cvt_pkrtz_f16_f32_e32 v7, v14, v15 ; 5E0E1F0E
exp 15, 2, 1, 0, 0, v4, v5, v0, v0 ; F800042F 00000504
exp 15, 3, 1, 1, 1, v6, v7, v0, v0 ; F8001C3F 00000706
s_endpgm ; BF810000
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
@@ -2917,9 +2917,14 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
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FREE(outputs);
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}
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struct si_ps_exports {
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unsigned num;
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LLVMValueRef args[10][9];
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};
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static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
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LLVMValueRef depth, LLVMValueRef stencil,
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LLVMValueRef samplemask)
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LLVMValueRef depth, LLVMValueRef stencil,
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LLVMValueRef samplemask, struct si_ps_exports *exp)
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{
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struct si_shader_context *ctx = si_shader_context(bld_base);
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struct lp_build_context *base = &bld_base->base;
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@@ -2965,14 +2970,13 @@ static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
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/* Specify which components to enable */
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args[0] = lp_build_const_int32(base->gallivm, mask);
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lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
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ctx->voidt, args, 9, 0);
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memcpy(exp->args[exp->num++], args, sizeof(args));
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}
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static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
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LLVMValueRef *color, unsigned index,
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unsigned samplemask_param,
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bool is_last)
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bool is_last, struct si_ps_exports *exp)
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{
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struct si_shader_context *ctx = si_shader_context(bld_base);
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struct lp_build_context *base = &bld_base->base;
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@@ -3018,8 +3022,7 @@ static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
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} else if (args[c][0] == bld_base->uint_bld.zero)
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continue; /* unnecessary NULL export */
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lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
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ctx->voidt, args[c], 9, 0);
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memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
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}
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} else {
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LLVMValueRef args[9];
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@@ -3033,11 +3036,19 @@ static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
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} else if (args[0] == bld_base->uint_bld.zero)
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return; /* unnecessary NULL export */
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lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
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ctx->voidt, args, 9, 0);
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memcpy(exp->args[exp->num++], args, sizeof(args));
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}
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}
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static void si_emit_ps_exports(struct si_shader_context *ctx,
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struct si_ps_exports *exp)
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{
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for (unsigned i = 0; i < exp->num; i++)
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lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
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"llvm.SI.export", ctx->voidt,
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exp->args[i], 9, 0);
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}
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static void si_export_null(struct lp_build_tgsi_context *bld_base)
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{
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struct si_shader_context *ctx = si_shader_context(bld_base);
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@@ -3069,6 +3080,7 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
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LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
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int last_color_export = -1;
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int i;
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struct si_ps_exports exp = {};
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/* Determine the last export. If MRTZ is present, it's always last.
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* Otherwise, find the last color export.
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@@ -3135,7 +3147,7 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
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si_export_mrt_color(bld_base, color, semantic_index,
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SI_PARAM_SAMPLE_COVERAGE,
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last_color_export == i);
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last_color_export == i, &exp);
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break;
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default:
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fprintf(stderr,
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@@ -3145,7 +3157,9 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
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}
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if (depth || stencil || samplemask)
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si_export_mrt_z(bld_base, depth, stencil, samplemask);
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si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
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si_emit_ps_exports(ctx, &exp);
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}
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/**
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@@ -7495,6 +7509,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen,
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LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
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int last_sgpr, num_params, i;
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bool status = true;
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struct si_ps_exports exp = {};
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si_init_shader_ctx(&ctx, sscreen, &shader, tm);
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ctx.type = PIPE_SHADER_FRAGMENT;
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@@ -7564,7 +7579,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen,
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si_export_mrt_color(bld_base, color, mrt,
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num_params - 1,
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mrt == last_color_export);
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mrt == last_color_export, &exp);
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}
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/* Process depth, stencil, samplemask. */
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@@ -7576,10 +7591,13 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen,
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samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
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if (depth || stencil || samplemask)
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si_export_mrt_z(bld_base, depth, stencil, samplemask);
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si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
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else if (last_color_export == -1)
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si_export_null(bld_base);
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if (exp.num)
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si_emit_ps_exports(&ctx, &exp);
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/* Compile. */
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LLVMBuildRetVoid(gallivm->builder);
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radeon_llvm_finalize_module(&ctx.radeon_bld);
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