AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965: Drop unnecessary inst->base_mrf = -1 assignments.

Browse Source 
These are now unnecessary, as base_mrf is -1 by default.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke
2016-06-22 17:14:05 -07:00
parent 3e04e3758e
commit 255cff76d9
2 changed files with 0 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_fs.cpp
-4
View File
@@ -3403,7 +3403,6 @@ fs_visitor::lower_uniform_pull_constant_loads()
*/
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7;
inst->src[1] = payload;
inst->base_mrf = -1;
invalidate_live_intervals();
} else {
@@ -3919,7 +3918,6 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
inst->src[0] = payload;
inst->resize_sources(1);
inst->base_mrf = -1;
} else {
/* Send from the MRF */
load = bld.LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F),
@@ -4365,7 +4363,6 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
inst->src[1] = surface;
inst->src[2] = sampler;
inst->resize_sources(3);
inst->base_mrf = -1;
inst->mlen = mlen;
inst->header_size = header_size;
@@ -6110,7 +6107,6 @@ fs_visitor::run_tcs_single_patch()
fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
bld.null_reg_ud(), payload);
inst->mlen = 3;
inst->base_mrf = -1;
inst->eot = true;
if (shader_time_index >= 0)
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
-12
View File
@@ -2133,7 +2133,6 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
/* Constant indexing - use global offset. */
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp_dst, icp_handle);
inst->offset = base_offset + offset_const->u32[0];
inst->base_mrf = -1;
inst->mlen = 1;
inst->regs_written = num_components * type_sz(tmp_dst.type) / 4;
} else {
@@ -2144,7 +2143,6 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp_dst, payload);
inst->offset = base_offset;
inst->base_mrf = -1;
inst->mlen = 2;
inst->regs_written = num_components * type_sz(tmp_dst.type) / 4;
}
@@ -2415,7 +2413,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
inst->offset = imm_offset;
inst->mlen = 1;
inst->base_mrf = -1;
} else {
/* Indirect indexing - use per-slot offsets as well. */
const fs_reg srcs[] = { icp_handle, indirect_offset };
@@ -2424,7 +2421,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
inst->offset = imm_offset;
inst->base_mrf = -1;
inst->mlen = 2;
}
inst->regs_written = num_components * type_sz(dst.type) / 4;
@@ -2497,7 +2493,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, patch_handle);
inst->offset = 0;
inst->mlen = 1;
inst->base_mrf = -1;
inst->regs_written = 4;
/* dst.xy = tmp.wz */
@@ -2510,7 +2505,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, patch_handle);
inst->offset = 1;
inst->mlen = 1;
inst->base_mrf = -1;
inst->regs_written = 1;
break;
case GL_ISOLINES:
@@ -2529,7 +2523,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, patch_handle);
inst->offset = 1;
inst->mlen = 1;
inst->base_mrf = -1;
inst->regs_written = 4;
/* Reswizzle: WZYX */
@@ -2562,7 +2555,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, patch_handle);
inst->offset = imm_offset;
inst->mlen = 1;
inst->base_mrf = -1;
inst->regs_written = instr->num_components;
}
} else {
@@ -2577,7 +2569,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
inst->offset = imm_offset;
inst->mlen = 2;
inst->base_mrf = -1;
inst->regs_written = instr->num_components;
}
break;
@@ -2744,7 +2735,6 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
fs_inst *inst = bld.emit(opcode, bld.null_reg_ud(), payload);
inst->offset = imm_offset;
inst->mlen = mlen;
inst->base_mrf = -1;
/* If this is a 64-bit attribute, select the next two 64-bit channels
* to be handled in the next iteration.
@@ -2858,7 +2848,6 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dest, patch_handle);
inst->mlen = 1;
inst->offset = imm_offset;
inst->base_mrf = -1;
inst->regs_written = instr->num_components;
}
} else {
@@ -2873,7 +2862,6 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest, payload);
inst->mlen = 2;
inst->offset = imm_offset;
inst->base_mrf = -1;
inst->regs_written = instr->num_components;
}
break;