AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965: fix depth test on sandybridge

Browse Source 
This includes several corrections for fixing depth test on sandybridge.
Fix wrong bits definition in depth stencil state. Fix wrong order of
state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use
buffer width parameter in depth buffer setting.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Zhenyu Wang
2010-08-31 09:54:44 +08:00
parent be7816f2b7
commit 24ff42e7d5
3 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_misc_state.c
+1 -1
View File
@@ -295,7 +295,7 @@ static void emit_depthbuffer(struct brw_context *brw)
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
((region->width - 1) << 6) |
((region->height - 1) << 19));
OUT_BATCH(0);
src/mesa/drivers/dri/i965/brw_structs.h
+1 -1
View File
@@ -750,7 +750,7 @@ struct gen6_depth_stencil_state
} ds1;
struct {
GLuint pad0:25;
GLuint pad0:26;
GLuint depth_write_enable:1;
GLuint depth_test_func:3;
GLuint pad1:1;
src/mesa/drivers/dri/i965/gen6_cc.c
+1 -1
View File
@@ -267,9 +267,9 @@ static void upload_cc_state_pointers(struct brw_context *brw)
BEGIN_BATCH(4);
OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);