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iris: some dirty fixes

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two scissor bits, constants not being flagged, ZeroRTA, clip not being
flagged
This commit is contained in:
Kenneth Graunke
2018-06-15 16:22:58 -07:00
parent ccf37c7da9
commit 23987df412
3 changed files with 13 additions and 5 deletions
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src/gallium/drivers/iris/iris_context.h
+1 -1
View File
@@ -54,7 +54,7 @@ struct blorp_params;
#define IRIS_DIRTY_BLEND_STATE (1ull << 7)
#define IRIS_DIRTY_RASTER (1ull << 8)
#define IRIS_DIRTY_CLIP (1ull << 9)
#define IRIS_DIRTY_SCISSOR (1ull << 10)
// XXX: define IRIS_DIRTY_ (1ull << 10)
#define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
#define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
#define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
src/gallium/drivers/iris/iris_program_cache.c
+3 -2
View File
@@ -98,9 +98,10 @@ dirty_flag_for_cache(enum iris_program_cache_id cache_id)
{
assert(cache_id <= MESA_SHADER_STAGES);
// XXX: ugly
// XXX: ugly...
// XXX: CLIP: toggle if barycentric modes has any NONPERSPECTIVE or not
if (cache_id == IRIS_CACHE_FS)
return IRIS_DIRTY_WM | IRIS_DIRTY_FS;
return IRIS_DIRTY_WM | IRIS_DIRTY_FS | IRIS_DIRTY_CLIP;
return IRIS_DIRTY_VS << cache_id;
}
src/gallium/drivers/iris/iris_state.c
+9 -2
View File
@@ -725,6 +725,7 @@ iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
ice->state.cso_rast = new_cso;
ice->state.dirty |= IRIS_DIRTY_RASTER;
ice->state.dirty |= IRIS_DIRTY_CLIP;
}
static uint32_t
@@ -1289,6 +1290,10 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
}
if ((cso->layers == 0) == (state->layers == 0)) {
ice->state.dirty |= IRIS_DIRTY_CLIP;
}
util_copy_framebuffer_state(cso, state);
struct iris_depth_buffer_state *cso_z =
@@ -1398,6 +1403,7 @@ iris_set_constant_buffer(struct pipe_context *ctx,
pipe_resource_reference(&cbuf->surface_state_resource, NULL);
}
ice->state.dirty |= IRIS_DIRTY_CONSTANTS_VS << stage;
// XXX: maybe not necessary all the time...?
ice->state.dirty |= IRIS_DIRTY_BINDINGS_VS << stage;
}
@@ -2255,7 +2261,7 @@ iris_restore_context_saved_bos(struct iris_context *ice,
iris_use_optional_res(batch, ice->state.last_res.color_calc, false);
}
if (clean & IRIS_DIRTY_SCISSOR) {
if (clean & IRIS_DIRTY_SCISSOR_RECT) {
iris_use_optional_res(batch, ice->state.last_res.scissor, false);
}
@@ -2358,6 +2364,7 @@ iris_upload_render_state(struct iris_context *ice,
/* XXX: L3 State */
// XXX: this is only flagged at setup, we assume a static configuration
if (dirty & IRIS_DIRTY_URB) {
iris_upload_urb_config(ice, batch);
}
@@ -2610,7 +2617,7 @@ iris_upload_render_state(struct iris_context *ice,
iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
}
if (dirty & IRIS_DIRTY_SCISSOR) {
if (dirty & IRIS_DIRTY_SCISSOR_RECT) {
// XXX: allocate at set_scissor time?
uint32_t scissor_offset = ice->state.num_scissors == 0 ? 0 :
emit_state(batch, ice->state.dynamic_uploader,