anv/icl: Allow headerless sampler messages for pre-emptable contexts

It fixes simulator warnings in vulkancts tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/intel/genxml/gen11.xml

@@ -3635,4 +3635,9 @@
     <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="20" end="20" type="bool"/>
   </register>
 
+  <register name="SAMPLER_MODE" length="1" num="0x0e18c">
+    <field name="Headerless Message for Pre-emptable Contexts" start="5" end="5" type="bool"/>
+    <field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/>
+  </register>
+
 </genxml>

src/intel/vulkan/genX_state.c

@@ -157,6 +157,23 @@ genX(init_device_state)(struct anv_device *device)
    gen10_emit_wa_lri_to_cache_mode_zero(&batch);
 #endif
 
+#if GEN_GEN == 11
+   /* The default behavior of bit 5 "Headerless Message for Pre-emptable
+    * Contexts" in SAMPLER MODE register is set to 0, which means
+    * headerless sampler messages are not allowed for pre-emptable
+    * contexts. Set the bit 5 to 1 to allow them.
+    */
+   uint32_t sampler_mode;
+   anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
+                   .HeaderlessMessageforPreemptableContexts = true,
+                   .HeaderlessMessageforPreemptableContextsMask = true);
+
+    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+      lri.RegisterOffset = GENX(SAMPLER_MODE_num);
+      lri.DataDWord      = sampler_mode;
+   }
+#endif
+
    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
     * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
     *