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ac,radeonsi: add sampler changes for Aldebaran

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- no 3D and cube textures
- no mipmapping
- no border color
- image_sample is the only supported opcode with a sampler (behaves like _lz)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>
This commit is contained in:
Marek Olšák
2021-03-02 23:36:20 -05:00
committed by Marge Bot
parent 381d3a5a38
commit 230a6dc55d
16 changed files with 95 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_gpu_info.c
+2
View File
@@ -956,6 +956,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->use_late_alloc = info->family != CHIP_KABINI;
}
info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS;
info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
info->min_wave64_vgpr_alloc = 4;
@@ -1037,6 +1038,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication);
fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
fprintf(f, "Display features:\n");
fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
src/amd/common/ac_gpu_info.h
+1
View File
@@ -76,6 +76,7 @@ struct radeon_info {
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool has_32bit_predication;
bool has_3d_cube_border_color_mipmap;
/* Display features. */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
src/amd/llvm/ac_llvm_build.c
+2
View File
@@ -57,6 +57,7 @@ struct ac_llvm_flow {
*/
void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *compiler,
enum chip_class chip_class, enum radeon_family family,
const struct radeon_info *info,
enum ac_float_mode float_mode, unsigned wave_size,
unsigned ballot_mask_bits)
{
@@ -64,6 +65,7 @@ void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *
ctx->chip_class = chip_class;
ctx->family = family;
ctx->info = info;
ctx->wave_size = wave_size;
ctx->ballot_mask_bits = ballot_mask_bits;
ctx->float_mode = float_mode;
src/amd/llvm/ac_llvm_build.h
+2
View File
@@ -133,6 +133,7 @@ struct ac_llvm_context {
enum chip_class chip_class;
enum radeon_family family;
const struct radeon_info *info;
unsigned wave_size;
unsigned ballot_mask_bits;
@@ -144,6 +145,7 @@ struct ac_llvm_context {
void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *compiler,
enum chip_class chip_class, enum radeon_family family,
const struct radeon_info *info,
enum ac_float_mode float_mode, unsigned wave_size,
unsigned ballot_mask_bits);
src/amd/llvm/ac_nir_to_llvm.c
+5 -1
View File
@@ -22,7 +22,7 @@
*/
#include "ac_nir_to_llvm.h"
#include "ac_gpu_info.h"
#include "ac_binary.h"
#include "ac_llvm_build.h"
#include "ac_llvm_util.h"
@@ -1504,6 +1504,10 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, const nir_te
break;
}
/* Aldebaran doesn't have image_sample_lz, but image_sample behaves like lz. */
if (!ctx->ac.info->has_3d_cube_border_color_mipmap)
args->level_zero = false;
if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= GFX8) {
nir_deref_instr *texture_deref_instr = get_tex_texture_deref(instr);
nir_variable *var = nir_deref_instr_get_variable(texture_deref_instr);
src/amd/vulkan/radv_nir_to_llvm.c
+3 -2
View File
@@ -3873,7 +3873,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
}
ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
args->options->family, float_mode,
args->options->family, args->options->info, float_mode,
args->shader_info->wave_size,
args->shader_info->ballot_bit_size);
ctx.context = ctx.ac.context;
@@ -4358,7 +4358,8 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
assert(args->is_gs_copy_shader);
ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
args->options->family, args->options->info,
AC_FLOAT_MODE_DEFAULT, 64, 64);
ctx.context = ctx.ac.context;
ctx.stage = MESA_SHADER_VERTEX;
src/amd/vulkan/radv_shader.c
+1
View File
@@ -1360,6 +1360,7 @@ shader_variant_compile(struct radv_device *device,
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
options->info = &device->physical_device->rad_info;
options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
src/amd/vulkan/radv_shader.h
+1
View File
@@ -149,6 +149,7 @@ struct radv_nir_compiler_options {
bool wgp_mode;
enum radeon_family family;
enum chip_class chip_class;
const struct radeon_info *info;
uint32_t tess_offchip_block_dw_size;
uint32_t address32_hi;
src/gallium/drivers/radeonsi/si_compute.c
+12 -6
View File
@@ -347,8 +347,6 @@ static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsi
void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_begin(cs);
radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
/* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
@@ -366,8 +364,11 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
*/
radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed)
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
}
if (sctx->chip_class >= GFX7) {
@@ -383,9 +384,14 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
}
/* Set the pointer to border colors. */
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2, false);
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
/* Aldebaran doesn't support border colors. */
if (sctx->border_color_buffer) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2, false);
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
}
}
/* cs_preamble_state initializes this for the gfx queue, so only do this
src/gallium/drivers/radeonsi/si_get.c
+10 -4
View File
@@ -70,14 +70,12 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
case PIPE_CAP_VERTEX_SHADER_SATURATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_NPOT_TEXTURES:
@@ -92,7 +90,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_DRAW_INDIRECT:
case PIPE_CAP_CLIP_HALFZ:
@@ -121,7 +118,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_CLEAR_TEXTURE:
@@ -169,6 +165,12 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_GLSL_ZERO_INIT:
return 2;
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_CUBE_MAP_ARRAY:
return sscreen->info.has_3d_cube_border_color_mipmap;
case PIPE_CAP_QUERY_SO_OVERFLOW:
return !sscreen->use_ngg_streamout;
@@ -281,8 +283,12 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
return 16384;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
if (!sscreen->info.has_3d_cube_border_color_mipmap)
return 0;
return 15; /* 16384 */
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
if (!sscreen->info.has_3d_cube_border_color_mipmap)
return 0;
if (sscreen->info.chip_class >= GFX10)
return 14;
/* textures support 8192, but layered rendering supports 2048 */
src/gallium/drivers/radeonsi/si_gfx_cs.c
+4 -2
View File
@@ -393,8 +393,10 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
if (ctx->chip_class == GFX10 && ctx->ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
ctx->flags |= SI_CONTEXT_VGT_FLUSH;
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer,
RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
if (ctx->border_color_buffer) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer,
RADEON_USAGE_READ, RADEON_PRIO_BORDER_COLORS);
}
if (ctx->shadowed_regs) {
radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->shadowed_regs,
RADEON_USAGE_READWRITE,
src/gallium/drivers/radeonsi/si_pipe.c
+13 -11
View File
@@ -529,19 +529,21 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
}
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
if (sscreen->info.has_3d_cube_border_color_mipmap) {
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
sctx->border_color_buffer = si_resource(pipe_buffer_create(
screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_buffer = si_resource(pipe_buffer_create(
screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_MAP_WRITE);
if (!sctx->border_color_map)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf, NULL, PIPE_MAP_WRITE);
if (!sctx->border_color_map)
goto fail;
}
sctx->ngg = sscreen->use_ngg;
src/gallium/drivers/radeonsi/si_shader_llvm.c
+1 -1
View File
@@ -134,7 +134,7 @@ void si_llvm_context_init(struct si_shader_context *ctx, struct si_screen *sscre
ctx->compiler = compiler;
ac_llvm_context_init(&ctx->ac, compiler, sscreen->info.chip_class, sscreen->info.family,
AC_FLOAT_MODE_DEFAULT_OPENGL, wave_size, 64);
&sscreen->info, AC_FLOAT_MODE_DEFAULT_OPENGL, wave_size, 64);
}
void si_llvm_create_func(struct si_shader_context *ctx, const char *name, LLVMTypeRef *return_types,
src/gallium/drivers/radeonsi/si_state.c
+29
View File
@@ -1866,6 +1866,20 @@ out_unknown:
return ~0;
}
static unsigned is_wrap_mode_legal(struct si_screen *screen, unsigned wrap)
{
if (!screen->info.has_3d_cube_border_color_mipmap) {
switch (wrap) {
case PIPE_TEX_WRAP_CLAMP:
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
return false;
}
}
return true;
}
static unsigned si_tex_wrap(unsigned wrap)
{
switch (wrap) {
@@ -2169,6 +2183,10 @@ static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format
return false;
}
if ((target == PIPE_TEXTURE_3D || target == PIPE_TEXTURE_CUBE) &&
!sscreen->info.has_3d_cube_border_color_mipmap)
return NULL;
if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
return false;
@@ -4468,6 +4486,17 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
return NULL;
}
/* Validate inputs. */
if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
!is_wrap_mode_legal(sscreen, state->wrap_t) ||
!is_wrap_mode_legal(sscreen, state->wrap_r) ||
(!sscreen->info.has_3d_cube_border_color_mipmap &&
(state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE ||
state->max_anisotropy > 0))) {
assert(0);
return NULL;
}
#ifndef NDEBUG
rstate->magic = SI_SAMPLER_STATE_MAGIC;
#endif
src/gallium/drivers/radeonsi/si_texture.c
+8
View File
@@ -896,6 +896,14 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
struct si_resource *resource;
struct si_screen *sscreen = (struct si_screen *)screen;
if (!sscreen->info.has_3d_cube_border_color_mipmap &&
(base->last_level > 0 ||
base->target == PIPE_TEXTURE_3D ||
base->target == PIPE_TEXTURE_CUBE)) {
assert(0);
return NULL;
}
tex = CALLOC_STRUCT(si_texture);
if (!tex)
goto error;
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+1
View File
@@ -607,6 +607,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.num_physical_wave64_vgprs_per_simd = 256;
/* Potential hang on Kabini: */
ws->info.use_late_alloc = ws->info.family != CHIP_KABINI;
ws->info.has_3d_cube_border_color_mipmap = true;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;