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nir: remove manual nir_store_global

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Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37959>
This commit is contained in:
Georg Lehmann
2025-10-20 17:26:20 +02:00
parent 9e41a7c139
commit 2306cba65b
16 changed files with 84 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_debug_nir.c
+3 -4
View File
@@ -181,7 +181,7 @@ radv_build_printf_args(nir_builder *b, nir_def *cond, const char *format_string,
nir_def *addr = nir_iadd_imm(b, nir_u2u64(b, offset), device->printf.buffer_addr);
/* header */
nir_store_global(b, addr, 4, nir_ior_imm(b, active_invocation_count, format_index << 16), 1);
nir_store_global(b, nir_ior_imm(b, active_invocation_count, format_index << 16), addr);
addr = nir_iadd_imm(b, addr, 4);
for (uint32_t i = 0; i < argc; i++) {
@@ -190,10 +190,9 @@ radv_build_printf_args(nir_builder *b, nir_def *cond, const char *format_string,
if (arg->divergent) {
nir_def *invocation_index = nir_mbcnt_amd(b, ballot, nir_imm_int(b, 0));
nir_store_global(
b, nir_iadd(b, addr, nir_u2u64(b, nir_imul_imm(b, invocation_index, format.element_sizes[i]))), 4, arg,
1);
b, arg, nir_iadd(b, addr, nir_u2u64(b, nir_imul_imm(b, invocation_index, format.element_sizes[i]))));
} else {
nir_store_global(b, addr, 4, arg, 1);
nir_store_global(b, arg, addr, );
}
addr = nir_iadd(b, addr, nir_u2u64(b, strides[i]));
src/asahi/vulkan/hk_cmd_meta.c
+1 -2
View File
@@ -416,8 +416,7 @@ load_store_formatted(nir_builder *b, nir_def *base, nir_def *index,
raw = nir_trim_vector(b, raw, blocksize_B / 4);
}
nir_store_global(b, addr, blocksize_B, raw,
nir_component_mask(raw->num_components));
nir_store_global(b, raw, addr, .align_mul = blocksize_B);
} else {
nir_def *raw = nir_load_global(b, DIV_ROUND_UP(blocksize_B, 4),
MIN2(32, blocksize_B * 8), addr,
src/compiler/nir/nir_builder.h
-16
View File
@@ -2062,22 +2062,6 @@ nir_store_array_var_imm(nir_builder *build, nir_variable *var, int64_t index,
nir_store_deref(build, deref, value, writemask);
}
#undef nir_store_global
static inline void
nir_store_global(nir_builder *build, nir_def *addr, unsigned align,
nir_def *value, nir_component_mask_t write_mask)
{
nir_intrinsic_instr *store =
nir_intrinsic_instr_create(build->shader, nir_intrinsic_store_global);
store->num_components = value->num_components;
store->src[0] = nir_src_for_ssa(value);
store->src[1] = nir_src_for_ssa(addr);
nir_intrinsic_set_write_mask(store,
write_mask & BITFIELD_MASK(value->num_components));
nir_intrinsic_set_align(store, align, 0);
nir_builder_instr_insert(build, &store->instr);
}
#undef nir_load_global_constant
static inline nir_def *
nir_load_global_constant(nir_builder *build, nir_def *addr, unsigned align,
src/compiler/nir/nir_lower_printf.c
+4 -5
View File
@@ -51,8 +51,7 @@ lower_printf_intrin(nir_builder *b, nir_intrinsic_instr *prntf, void *_options)
* uint32_t data[];
*/
if (prntf->intrinsic == nir_intrinsic_printf_abort) {
nir_store_global(b, nir_iadd_imm(b, buffer_addr, 4), 4, nir_imm_int(b, 1),
nir_component_mask(1));
nir_store_global(b, nir_imm_int(b, 1), nir_iadd_imm(b, buffer_addr, 4));
/* Halt is a jump instruction so can only appear at the end of a block.
* The abort might be in the middle of a block. So, wrap the halt and let
@@ -259,7 +258,7 @@ nir_vprintf_fmt(nir_builder *b, unsigned ptr_bit_size, const char *fmt, va_list
nir_def *identifier = nir_imm_int(b, u_printf_hash(&info));
nir_def *store_addr =
nir_iadd(b, buffer_addr, nir_u2uN(b, buffer_offset, buffer_addr->bit_size));
nir_store_global(b, store_addr, 4, identifier, 0x1);
nir_store_global(b, identifier, store_addr);
/* Arguments */
va_copy(ap, aq);
@@ -267,8 +266,8 @@ nir_vprintf_fmt(nir_builder *b, unsigned ptr_bit_size, const char *fmt, va_list
for (unsigned a = 0; a < info.num_args; a++) {
nir_def *def = va_arg(ap, nir_def *);
nir_store_global(b, nir_iadd_imm(b, store_addr, store_offset),
4, def, nir_component_mask(def->num_components));
nir_store_global(b, def, nir_iadd_imm(b, store_addr, store_offset),
.align_mul = 4);
store_offset += info.arg_sizes[a];
}
src/compiler/nir/nir_lower_shader_calls.c
+2 -4
View File
@@ -1374,10 +1374,8 @@ lower_stack_instr_to_scratch(struct nir_builder *b, nir_instr *instr, void *data
nir_def *addr = nir_iadd_imm(b,
nir_load_scratch_base_ptr(b, 1, 64, 1),
nir_intrinsic_base(stack));
nir_store_global(b, addr,
nir_intrinsic_align_mul(stack),
data,
nir_component_mask(data->num_components));
nir_store_global(b, data, addr,
.align_mul = nir_intrinsic_align_mul(stack));
} else {
assert(state->address_format == nir_address_format_32bit_offset);
nir_store_scratch(b, data,
src/compiler/nir/tests/range_analysis_tests.cpp
+20 -20
View File
@@ -76,7 +76,7 @@ TEST_F(ssa_def_bits_used_test, iand_with_const_vector)
nir_def *src1 = nir_imm_int(b, 0xffffffff);
nir_alu_instr *alu = build_alu_instr(nir_op_iand, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -106,7 +106,7 @@ TEST_F(ssa_def_bits_used_test, ior_with_const_vector)
nir_def *src1 = nir_imm_int(b, 0xffffffff);
nir_alu_instr *alu = build_alu_instr(nir_op_ior, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -139,7 +139,7 @@ TEST_F(ssa_def_bits_used_test, extract_i16_with_const_index)
src1_imm[3]);
nir_alu_instr *alu = build_alu_instr(nir_op_extract_i16, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -171,7 +171,7 @@ TEST_F(ssa_def_bits_used_test, extract_u16_with_const_index)
src1_imm[3]);
nir_alu_instr *alu = build_alu_instr(nir_op_extract_u16, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -203,7 +203,7 @@ TEST_F(ssa_def_bits_used_test, extract_i8_with_const_index)
src1_imm[3]);
nir_alu_instr *alu = build_alu_instr(nir_op_extract_i8, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -235,7 +235,7 @@ TEST_F(ssa_def_bits_used_test, extract_u8_with_const_index)
src1_imm[3]);
nir_alu_instr *alu = build_alu_instr(nir_op_extract_u8, src0, src1);
nir_store_global(b, nir_undef(b, 1, 64), 4, &alu->def, 0x1);
nir_store_global(b, &alu->def, nir_undef(b, 1, 64));
ASSERT_NE((void *) 0, alu);
@@ -306,8 +306,8 @@ TEST_F(ssa_def_bits_used_test, ubfe_ibfe)
nir_def *alu1 = nir_ubfe_imm(b, load1, 14, 3);
nir_def *alu2 = nir_ibfe_imm(b, load2, 12, 7);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu1, 0x1);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu2, 0x1);
nir_store_global(b, alu1, nir_undef(b, 1, 64));
nir_store_global(b, alu2, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load1), BITFIELD_RANGE(14, 3));
EXPECT_EQ(nir_def_bits_used(load2), BITFIELD_RANGE(12, 7));
@@ -317,7 +317,7 @@ TEST_F(ssa_def_bits_used_test, ibfe_iand)
{
nir_def *load = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu = nir_iand_imm(b, nir_ibfe_imm(b, load, 14, 3), 0x80000000);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load), BITFIELD_BIT(16));
}
@@ -326,7 +326,7 @@ TEST_F(ssa_def_bits_used_test, ubfe_iand)
{
nir_def *load = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu = nir_iand_imm(b, nir_ubfe_imm(b, load, 14, 3), 0x2);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load), BITFIELD_BIT(15));
}
@@ -337,8 +337,8 @@ TEST_F(ssa_def_bits_used_test, ishr_signed)
nir_def *load2 = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu1 = nir_iand_imm(b, nir_ishr_imm(b, load1, 13), 0x80000000);
nir_def *alu2 = nir_iand_imm(b, nir_ishr_imm(b, load2, 13), 0x8000);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu1, 0x1);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu2, 0x1);
nir_store_global(b, alu1, nir_undef(b, 1, 64));
nir_store_global(b, alu2, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load1), BITFIELD_BIT(31)); /* last bit */
EXPECT_EQ(nir_def_bits_used(load2), BITFIELD_BIT(15 + 13)); /* not last bit */
@@ -354,9 +354,9 @@ TEST_F(ssa_def_bits_used_test, ushr_ishr_ishl)
nir_def *alu2 = nir_ishr_imm(b, load2, 11);
nir_def *alu3 = nir_ishl_imm(b, load3, 13);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu1, 0x1);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu2, 0x1);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu3, 0x1);
nir_store_global(b, alu1, nir_undef(b, 1, 64));
nir_store_global(b, alu2, nir_undef(b, 1, 64));
nir_store_global(b, alu3, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load1), BITFIELD_RANGE(7, 32 - 7));
EXPECT_EQ(nir_def_bits_used(load2), BITFIELD_RANGE(11, 32 - 11));
@@ -380,7 +380,7 @@ TEST_F(ssa_def_bits_used_test, u2u_i2i_iand)
for (unsigned i = 0; i < ARRAY_SIZE(ops); i++) {
load[i] = nir_load_global(b, 1, 64, nir_undef(b, 1, 64));
nir_def *alu = nir_iand_imm(b, ops[i](b, load[i]), 0x1020304050607080ull);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
}
EXPECT_EQ(nir_def_bits_used(load[0]), 0x80);
@@ -408,7 +408,7 @@ TEST_F(ssa_def_bits_used_test, u2u_i2i_upcast_bits)
nir_def *upcast = ops[i](b, load[i]);
/* Using one of the sing-extended bits implies using the last bit. */
nir_def *alu = nir_iand_imm(b, upcast, BITFIELD64_BIT(upcast->bit_size - 1));
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
}
EXPECT_EQ(nir_def_bits_used(load[0]), 0x0);
@@ -432,7 +432,7 @@ TEST_F(ssa_def_bits_used_test, iand_ior_ishl)
for (unsigned i = 0; i < ARRAY_SIZE(ops); i++) {
load[i] = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu = nir_ishl_imm(b, ops[i](b, load[i], 0x12345678), 8);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
}
EXPECT_EQ(nir_def_bits_used(load[0]), 0x345678);
@@ -443,7 +443,7 @@ TEST_F(ssa_def_bits_used_test, mov_iand)
{
nir_def *load = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu = nir_iand_imm(b, nir_mov(b, load), 0x8);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load), BITFIELD_BIT(3));
}
@@ -454,7 +454,7 @@ TEST_F(ssa_def_bits_used_test, bcsel_iand)
nir_def *load2 = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *load3 = nir_load_global(b, 1, 32, nir_undef(b, 1, 64));
nir_def *alu = nir_iand_imm(b, nir_bcsel(b, load1, load2, load3), 0x8);
nir_store_global(b, nir_undef(b, 1, 64), 4, alu, 0x1);
nir_store_global(b, alu, nir_undef(b, 1, 64));
EXPECT_EQ(nir_def_bits_used(load1), BITFIELD_BIT(0));
EXPECT_EQ(nir_def_bits_used(load2), BITFIELD_BIT(3));
src/gallium/drivers/panfrost/pan_mod_conv_cso.c
+5 -4
View File
@@ -73,7 +73,8 @@ static void
write_afbc_header(nir_builder *b, nir_def *buf, nir_def *idx, nir_def *hdr)
{
nir_def *offset = nir_imul_imm(b, idx, AFBC_HEADER_BYTES_PER_TILE);
nir_store_global(b, nir_iadd(b, buf, nir_u2u64(b, offset)), 16, hdr, 0xF);
nir_store_global(b, hdr, nir_iadd(b, buf, nir_u2u64(b, offset)),
.align_mul = 16);
}
static nir_def *
@@ -179,9 +180,9 @@ copy_superblock(nir_builder *b, nir_def *dst, nir_def *hdr_sz, nir_def *src,
nir_def *src_line = nir_iadd(b, src_bodyptr, nir_u2u64(b, offset));
nir_def *dst_line = nir_iadd(b, dst_bodyptr, nir_u2u64(b, offset));
nir_store_global(
b, dst_line, line_sz,
b,
nir_load_global(b, line_sz / 4, 32, src_line, .align_mul = line_sz),
~0);
dst_line, .align_mul = line_sz);
offset = nir_iadd_imm(b, offset, line_sz);
}
nir_store_var(b, offset_var, offset, 0x1);
@@ -223,7 +224,7 @@ panfrost_create_afbc_size_shader(struct panfrost_screen *screen,
nir_iadd(&b,
nir_imul_imm(&b, block_idx, sizeof(struct pan_afbc_payload_extent)),
nir_imm_int(&b, offsetof(struct pan_afbc_payload_extent, size))));
nir_store_global(&b, nir_iadd(&b, layout, offset), 4, size, 0x1);
nir_store_global(&b, size, nir_iadd(&b, layout, offset));
return b.shader;
}
src/intel/compiler/brw/brw_nir_lower_intersection_shader.c
+9 -12
View File
@@ -138,9 +138,9 @@ build_accept_ray(nir_builder *b)
/* Set the "valid" bit in mem_hit */
nir_def *ray_addr = brw_nir_rt_mem_hit_addr(b, false /* committed */);
nir_def *flags_dw_addr = nir_iadd_imm(b, ray_addr, 12);
nir_store_global(b, flags_dw_addr, 4,
nir_ior(b, nir_load_global(b, 1, 32, flags_dw_addr),
nir_imm_int(b, 1 << 16)), 0x1 /* write_mask */);
nir_store_global(b, nir_ior(b, nir_load_global(b, 1, 32, flags_dw_addr),
nir_imm_int(b, 1 << 16)),
flags_dw_addr);
nir_accept_ray_intersection(b);
}
@@ -241,7 +241,7 @@ brw_nir_lower_intersection_shader(nir_shader *intersection,
nir_def *ray_addr =
brw_nir_rt_mem_ray_addr(b, brw_nir_rt_stack_addr(b), BRW_RT_BVH_LEVEL_WORLD);
nir_store_global(b, nir_iadd_imm(b, ray_addr, 16 + 12), 4, hit_t, 0x1);
nir_store_global(b, hit_t, nir_iadd_imm(b, ray_addr, 16 + 12));
if (devinfo->ver >= 30) {
/* For Xe3+, the most significant 8 bits of the second
* DW in the potential hit are used to store
@@ -262,16 +262,13 @@ brw_nir_lower_intersection_shader(nir_shader *intersection,
* gl_HitKindEXT that uses more than 24bits.
*/
nir_def *hit_kind_24b = nir_iand_imm(b, hit_kind, 0xffffff);
nir_store_global(b, t_addr, 4,
nir_vec2(b,
nir_fmin(b, hit_t, hit_in.t),
nir_ior(b, hit_group_index_0, hit_kind_24b)),
0x3);
nir_store_global(b, nir_vec2(b, nir_fmin(b, hit_t, hit_in.t),
nir_ior(b, hit_group_index_0, hit_kind_24b)),
t_addr);
} else {
nir_store_global(b, t_addr, 4,
nir_vec2(b, nir_fmin(b, hit_t, hit_in.t), hit_kind),
0x3);
nir_store_global(b, nir_vec2(b, nir_fmin(b, hit_t, hit_in.t), hit_kind),
t_addr);
}
/* There may be multiple reportIntersection() calls in
src/intel/compiler/brw/brw_nir_lower_rt_intrinsics.c
+2 -2
View File
@@ -130,7 +130,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
if (stack_size > 0) {
nir_def *child_stack_offset =
nir_iadd_imm(b, stack_base_offset, stack_size);
nir_store_global(b, hotzone_addr, 16, child_stack_offset, 0x1);
nir_store_global(b, child_stack_offset, hotzone_addr, .align_mul = 16);
}
nir_instr_remove(instr);
break;
@@ -146,7 +146,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
if (stack_size > 0) {
stack_base_offset =
nir_iadd_imm(b, stack_base_offset, -stack_size);
nir_store_global(b, hotzone_addr, 16, stack_base_offset, 0x1);
nir_store_global(b, stack_base_offset, hotzone_addr, .align_mul = 16);
stack_base_addr = nir_iadd(b, thread_stack_base_addr,
nir_u2u64(b, stack_base_offset));
}
src/intel/compiler/brw/brw_nir_rt.c
+4 -4
View File
@@ -109,7 +109,7 @@ lower_rt_io_derefs(nir_shader *shader, const struct intel_device_info *devinfo)
brw_nir_rt_stack_addr(&b),
stage == MESA_SHADER_CLOSEST_HIT,
devinfo);
nir_store_global(&b, hit_attrib_addr, 4, tri_bary, 0x3);
nir_store_global(&b, tri_bary, hit_attrib_addr);
}
nir_pop_if(&b, NULL);
@@ -470,12 +470,12 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
nir_def *launch_size = nir_load_ray_launch_size(&b);
nir_push_if(&b, nir_ball(&b, nir_ult(&b, launch_id, launch_size)));
{
nir_store_global(&b, brw_nir_rt_sw_hotzone_addr(&b, devinfo), 16,
nir_vec4(&b, nir_imm_int(&b, 0), /* Stack ptr */
nir_store_global(&b, nir_vec4(&b, nir_imm_int(&b, 0), /* Stack ptr */
nir_channel(&b, launch_id, 0),
nir_channel(&b, launch_id, 1),
nir_channel(&b, launch_id, 2)),
0xf /* write mask */);
brw_nir_rt_sw_hotzone_addr(&b, devinfo),
.align_mul = 16);
brw_nir_btd_spawn(&b, raygen_bsr_addr);
}
src/nouveau/vulkan/nvk_cmd_indirect.c
+1 -1
View File
@@ -122,7 +122,7 @@ store_global_dw(nir_builder *b, nir_def *addr, uint32_t offset_dw,
nir_def *data)
{
assert(data->bit_size == 32 && data->num_components == 1);
nir_store_global(b, nir_iadd_imm(b, addr, offset_dw * 4), 4, data, 0x1);
nir_store_global(b, data, nir_iadd_imm(b, addr, offset_dw * 4));
}
static void
src/panfrost/util/pan_lower_xfb.c
+1 -1
View File
@@ -54,7 +54,7 @@ lower_xfb_output(nir_builder *b, nir_intrinsic_instr *intr,
nir_def *src = intr->src[0].ssa;
nir_component_mask_t mask = nir_component_mask(num_components);
nir_def *value = nir_channels(b, src, mask << start_component);
nir_store_global(b, addr, 4, value, mask);
nir_store_global(b, value, addr);
}
static bool
src/panfrost/vulkan/bifrost/panvk_vX_meta_desc_copy.c
+19 -15
View File
@@ -103,8 +103,8 @@ set_to_table_copy(nir_builder *b, nir_def *set_ptr, nir_def *set_desc_count,
nir_def *desc = nir_load_global(b, element_size / 4, 32,
nir_iadd(b, set_ptr, src_offset),
.align_mul = element_size);
nir_store_global(b, nir_iadd(b, table_ptr, dst_offset), element_size,
desc, ~0);
nir_store_global(b, desc, nir_iadd(b, table_ptr, dst_offset),
.align_mul = element_size);
}
nir_push_else(b, NULL);
{
@@ -116,8 +116,8 @@ set_to_table_copy(nir_builder *b, nir_def *set_ptr, nir_def *set_desc_count,
};
nir_def *desc = nir_build_imm(b, element_size / 4, 32, v);
nir_store_global(b, nir_iadd(b, table_ptr, dst_offset), element_size,
desc, ~0);
nir_store_global(b, desc, nir_iadd(b, table_ptr, dst_offset),
.align_mul = element_size);
}
nir_pop_if(b, NULL);
}
@@ -159,9 +159,10 @@ set_to_table_img_copy(nir_builder *b, nir_def *set_ptr, nir_def *set_desc_count,
nir_def *attrib_desc = nir_vec2(b, attrib_w1, nir_imm_int(b, 0));
nir_store_global(b, nir_iadd(b, attrib_table_ptr, attrib_offset),
pan_size(ATTRIBUTE), attrib_desc,
nir_component_mask(attrib_comps));
nir_store_global(b, attrib_desc,
nir_iadd(b, attrib_table_ptr, attrib_offset),
.align_mul = pan_size(ATTRIBUTE),
.write_mask = nir_component_mask(attrib_comps));
nir_def *attrib_buf_desc = nir_vec8(
b, nir_channel(b, src_desc, 0), nir_channel(b, src_desc, 1),
@@ -169,9 +170,10 @@ set_to_table_img_copy(nir_builder *b, nir_def *set_ptr, nir_def *set_desc_count,
nir_channel(b, src_desc, 3), nir_channel(b, src_desc, 4),
nir_channel(b, src_desc, 5), nir_channel(b, src_desc, 6),
nir_channel(b, src_desc, 7));
nir_store_global(b, nir_iadd(b, attrib_buf_table_ptr, attrib_buf_offset),
element_size, attrib_buf_desc,
nir_component_mask(attrib_buf_comps));
nir_store_global(b, attrib_buf_desc,
nir_iadd(b, attrib_buf_table_ptr, attrib_buf_offset),
.align_mul = element_size,
.write_mask = nir_component_mask(attrib_buf_comps));
}
nir_push_else(b, NULL);
{
@@ -185,11 +187,13 @@ set_to_table_img_copy(nir_builder *b, nir_def *set_ptr, nir_def *set_desc_count,
nir_def *desc =
nir_build_imm(b, MAX2(attrib_buf_comps, attrib_comps), 32, v);
nir_store_global(b, nir_iadd(b, attrib_buf_table_ptr, attrib_buf_offset),
pan_size(ATTRIBUTE), desc,
nir_component_mask(attrib_buf_comps));
nir_store_global(b, nir_iadd(b, attrib_table_ptr, attrib_offset),
element_size, desc, nir_component_mask(attrib_comps));
nir_store_global(b, desc,
nir_iadd(b, attrib_buf_table_ptr, attrib_buf_offset),
.align_mul = pan_size(ATTRIBUTE),
.write_mask = nir_component_mask(attrib_buf_comps));
nir_store_global(b, desc, nir_iadd(b, attrib_table_ptr, attrib_offset),
.align_mul = element_size,
.write_mask = nir_component_mask(attrib_comps));
}
nir_pop_if(b, NULL);
}
src/poly/nir/poly_nir_lower_gs.c
+5 -7
View File
@@ -383,7 +383,7 @@ write_xfb_counts(nir_builder *b, nir_intrinsic_instr *intr,
nir_imm_int(b, state->info->count_words), id);
if (state->info->prefix_sum) {
nir_store_global(b, addr, 4, intr->src[2].ssa, nir_component_mask(1));
nir_store_global(b, intr->src[2].ssa, addr);
} else {
nir_global_atomic(b, 32, addr, intr->src[2].ssa,
.atomic_op = nir_atomic_op_iadd);
@@ -762,7 +762,6 @@ create_gs_rast_shader(const nir_shader *gs, const struct lower_gs_state *state)
{
unsigned buffer = output.buffer;
unsigned stride = xfb->buffers[buffer].stride;
unsigned count = util_bitcount(output.component_mask);
nir_variable *var = rs.selected.outputs[output.location];
nir_def *value =
@@ -781,9 +780,8 @@ create_gs_rast_shader(const nir_shader *gs, const struct lower_gs_state *state)
nir_imm_int(b, buffer), nir_imm_int(b, stride),
nir_imm_int(b, output.offset));
nir_store_global(b, addr, 4,
nir_channels(b, value, output.component_mask),
nir_component_mask(count));
nir_store_global(
b, nir_channels(b, value, output.component_mask), addr);
}
nir_pop_if(b, NULL);
nir_pop_if(b, NULL);
@@ -1442,8 +1440,8 @@ lower_vs_before_gs(nir_builder *b, nir_intrinsic_instr *intr, void *data)
assert(nir_src_bit_size(intr->src[0]) == 32);
addr = nir_iadd_imm(b, addr, nir_intrinsic_component(intr) * 4);
nir_store_global(b, addr, 4, intr->src[0].ssa,
nir_intrinsic_write_mask(intr));
nir_store_global(b, intr->src[0].ssa, addr,
.write_mask = nir_intrinsic_write_mask(intr));
return true;
}
src/poly/nir/poly_nir_lower_tess.c
+6 -4
View File
@@ -142,14 +142,16 @@ lower_tcs_impl(nir_builder *b, nir_intrinsic_instr *intr)
nir_intrinsic_io_semantics(intr).location !=
VARYING_SLOT_TESS_LEVEL_INNER);
nir_store_global(b, tcs_out_addr(b, intr, nir_undef(b, 1, 32)), 4,
intr->src[0].ssa, nir_intrinsic_write_mask(intr));
nir_store_global(b, intr->src[0].ssa,
tcs_out_addr(b, intr, nir_undef(b, 1, 32)),
.write_mask = nir_intrinsic_write_mask(intr));
return NIR_LOWER_INSTR_PROGRESS_REPLACE;
}
case nir_intrinsic_store_per_vertex_output: {
nir_store_global(b, tcs_out_addr(b, intr, intr->src[1].ssa), 4,
intr->src[0].ssa, nir_intrinsic_write_mask(intr));
nir_store_global(b, intr->src[0].ssa,
tcs_out_addr(b, intr, intr->src[1].ssa),
.write_mask = nir_intrinsic_write_mask(intr));
return NIR_LOWER_INSTR_PROGRESS_REPLACE;
}
src/vulkan/runtime/vk_meta_copy_fill_update.c
+2 -2
View File
@@ -994,8 +994,8 @@ build_image_to_buffer_shader(const struct vk_meta_device *meta,
* that's fine because we pass a write_mask to store_global.
*/
assert(texel->num_components >= comp_count);
nir_store_global(b, copy_img_buf_addr(b, buf_pfmt, copy_id),
comp_sz / 8, texel, nir_component_mask(comp_count));
nir_store_global(b, texel, copy_img_buf_addr(b, buf_pfmt, copy_id),
.write_mask = nir_component_mask(comp_count));
nir_pop_if(b, NULL);