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intel/genxml: Add ROW_INSTDONE register.

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Rafael Antognolli
2018-03-21 11:42:21 -07:00
parent 4c0ae36143
commit 227edf05f3
6 changed files with 114 additions and 0 deletions
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src/intel/genxml/gen10.xml
+18
View File
@@ -3486,6 +3486,24 @@
<field name="SFBE Done" start="25" end="25" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
src/intel/genxml/gen11.xml
+18
View File
@@ -3482,6 +3482,24 @@
<field name="SFBE Done" start="25" end="25" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
src/intel/genxml/gen7.xml
+20
View File
@@ -2416,6 +2416,26 @@
<field name="VSC Done" start="16" end="16" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DC Done" start="2" end="2" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="GW Done" start="8" end="8" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="MA0 Done SS0" start="20" end="20" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done" start="25" end="25" type="bool"/>
</register>
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
src/intel/genxml/gen75.xml
+22
View File
@@ -2886,6 +2886,28 @@
<field name="SARB Done" start="15" end="15" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DC Done" start="2" end="2" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="GW Done" start="8" end="8" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU04 Done SS0" start="20" end="20" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="EU14 Done SS0" start="25" end="25" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
src/intel/genxml/gen8.xml
+18
View File
@@ -3147,6 +3147,24 @@
<field name="TDC Done" start="24" end="24" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
src/intel/genxml/gen9.xml
+18
View File
@@ -3432,6 +3432,24 @@
<field name="TDC Done" start="24" end="24" type="bool"/>
</register>
<register name="ROW_INSTDONE" length="1" num="0xe164">
<field name="BC Done" start="0" end="0" type="bool"/>
<field name="PSD Done" start="1" end="1" type="bool"/>
<field name="DAPR Done" start="3" end="3" type="bool"/>
<field name="TDL Done" start="6" end="6" type="bool"/>
<field name="IC Done" start="12" end="12" type="bool"/>
<field name="MA0 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done SS0" start="16" end="16" type="bool"/>
<field name="EU01 Done SS0" start="17" end="17" type="bool"/>
<field name="EU02 Done SS0" start="18" end="18" type="bool"/>
<field name="EU03 Done SS0" start="19" end="19" type="bool"/>
<field name="EU10 Done SS0" start="21" end="21" type="bool"/>
<field name="EU11 Done SS0" start="22" end="22" type="bool"/>
<field name="EU12 Done SS0" start="23" end="23" type="bool"/>
<field name="EU13 Done SS0" start="24" end="24" type="bool"/>
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>