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radv: set workgroup_size to 256 when patch control points is dynamic

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It's the maximum possible value. This is to ensure that compilers
don't optimize away barriers, like in ACO when workgroup_size is less
than or equal to wave_size, s_barrier is considered a no-op.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
This commit is contained in:
Samuel Pitoiset
2022-08-31 15:01:02 +02:00
committed by Marge Bot
parent 9373dbdfcc
commit 21d9390b0e
1 changed files with 17 additions and 11 deletions
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src/amd/vulkan/radv_shader_info.c
+17 -11
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@@ -1310,19 +1310,25 @@ radv_link_shaders_info(struct radv_device *device,
vs_stage->info.vs.as_ls = true;
vs_stage->info.workgroup_size =
ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level,
MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches,
pipeline_key->tcs.tess_input_vertices,
tcs_stage->info.tcs.tcs_vertices_out);
if (pipeline_key->dynamic_patch_control_points) {
/* Set the workgroup size to the maximum possible value to ensure that compilers don't
* optimize barriers.
*/
vs_stage->info.workgroup_size = 256;
tcs_stage->info.workgroup_size = 256;
} else {
vs_stage->info.workgroup_size =
ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level,
MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches,
pipeline_key->tcs.tess_input_vertices,
tcs_stage->info.tcs.tcs_vertices_out);
tcs_stage->info.workgroup_size =
ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level,
MESA_SHADER_TESS_CTRL, tcs_stage->info.num_tess_patches,
pipeline_key->tcs.tess_input_vertices,
tcs_stage->info.tcs.tcs_vertices_out);
tcs_stage->info.workgroup_size =
ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level,
MESA_SHADER_TESS_CTRL, tcs_stage->info.num_tess_patches,
pipeline_key->tcs.tess_input_vertices,
tcs_stage->info.tcs.tcs_vertices_out);
if (!(pipeline_key->dynamic_patch_control_points)) {
if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {
/* When the number of TCS input and output vertices are the same (typically 3):
* - There is an equal amount of LS and HS invocations