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freedreno/a6xx: disallow UBWC for x24s8

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Fixes:
  dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d
  dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d
  dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect

Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
2019-06-14 09:12:46 -07:00
committed by Rob Clark
parent 4e72abcd97
commit 21c795ab07
1 changed files with 15 additions and 4 deletions
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src/gallium/drivers/freedreno/a6xx/fd6_resource.c
+15 -4
View File
@@ -167,9 +167,20 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
* it can be tiled doesn't mean it can be compressed.
*/
static bool
ok_ubwc_format(enum a6xx_color_fmt fmt)
ok_ubwc_format(enum pipe_format pfmt)
{
switch (fmt) {
/* NOTE: both x24s8 and z24s8 map to RB6_X8Z24_UNORM, but UBWC
* does not seem to work properly when sampling x24s8.. possibly
* because we sample it as TFMT6_8_8_8_8_UINT.
*
* This could possibly be a hw limitation, or maybe something
* else wrong somewhere (although z24s8 blits and sampling with
* UBWC seem fine). Recheck on a later revision of a6xx
*/
if (pfmt == PIPE_FORMAT_X24S8_UINT)
return false;
switch (fd6_pipe2color(pfmt)) {
case RB6_R10G10B10A2_UINT:
case RB6_R10G10B10A2_UNORM:
case RB6_R11G11B10_FLOAT:
@@ -213,7 +224,7 @@ fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc)
uint32_t width = prsc->width0;
uint32_t height = prsc->height0;
if (!ok_ubwc_format(fd6_pipe2color(prsc->format)))
if (!ok_ubwc_format(prsc->format))
return 0;
/* limit things to simple single level 2d for now: */
@@ -271,7 +282,7 @@ fd6_validate_format(struct fd_context *ctx, struct fd_resource *rsc,
if (!rsc->ubwc_size)
return;
if (ok_ubwc_format(fd6_pipe2color(format)))
if (ok_ubwc_format(format))
return;
fd_resource_uncompress(ctx, rsc);