r600/sfn: on R600/R700 write a dummy pixel output if there is a gap

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9223

Fixes: 98d65120cb
  r600/sfn: Fix FS out handling

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23717>
This commit is contained in:
Gert Wollny
2023-06-19 08:53:49 +02:00
committed by Marge Bot
parent 0e728ea7b0
commit 201b46e487
2 changed files with 24 additions and 0 deletions
@@ -540,6 +540,8 @@ FragmentShader::emit_export_pixel(nir_intrinsic_instr& intr)
m_fs_write_all = false;
unsigned mask = (0xfu << (location * 4));
m_color_export_written_mask |= (1 << location);
/* If the i-th target format is set, all previous target formats must
* be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
/*/
@@ -589,6 +591,27 @@ FragmentShader::emit_load_sample_pos(nir_intrinsic_instr *instr)
void
FragmentShader::do_finalize()
{
/* On pre-evergreen not emtting something to all color exports that
* are enabled might lead to a hang.
* see: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9223
*/
if (chip_class() < ISA_CC_EVERGREEN) {
unsigned i = 0;
unsigned mask = m_color_export_mask;
while (mask & (1u << (4 * i))) {
if (!(m_color_export_written_mask & (1u << i))) {
RegisterVec4 value(0, false, {7, 7, 7, 7});
m_last_pixel_export = new ExportInstr(ExportInstr::pixel, i, value);
emit_instruction(m_last_pixel_export);
m_num_color_exports++;
if (m_export_highest < i)
m_export_highest = i;
}
++i;
}
}
if (!m_last_pixel_export) {
RegisterVec4 value(0, false, {7, 7, 7, 7});
m_last_pixel_export = new ExportInstr(ExportInstr::pixel, 0, value);
@@ -76,6 +76,7 @@ private:
unsigned m_num_color_exports;
unsigned m_color_export_mask;
ExportInstr *m_last_pixel_export;
unsigned m_color_export_written_mask{0};
std::bitset<s_max_interpolators> m_interpolators_used;
RegisterVec4 m_pos_input;