iris: Flush untyped dataport cache DC flush is requested on compute

KHR-GL46.texture_buffer.texture_buffer_operations_ssbo_writes writes
to an SSBO in a compute program, then issues a memory-barrier, which
causes us to add a DC-flush. Then a second compute program samples
from the SSBO written by the first compute program.

Although we expected the DC-flush to make the writes available to the
second compute program, on MTL this wasn't the case. Adding the
"Untyped Data-Port Cache Flush" fixes this.

The PRM indicates that compute programs must set "Untyped Data-Port
Cache Flush" to flush some LSC writes when flushing HDC. Although we
are setting DC-flush, and not HDC-flush, it does appear that the
following reference might also apply to DC-flush.

In the Intel(R) Arc(tm) A-Series Graphics and Intel Data Center GPU
Flex Series Open-Source Programmer's Reference Manual, Vol 2a: Command
Reference: Instructions, PIPE_CONTROL, HDC Pipeline Flush (DWord 0,
Bit 9), there is a programming note:

> When the "Pipeline Select" mode is set to "GPGPU", the LSC Untyped
> L1 cache flush is controlled by "Untyped Data-Port Cache Flush" bit
> in the PIPE_CONTROL command.

Ref: bd8e8d204d ("iris: Add missing untyped data port flush on PIPELINE_SELECT")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23176>

src/gallium/drivers/iris/iris_state.c

@@ -8827,7 +8827,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
 #if GFX_VERx10 >= 125
       pc.UntypedDataPortCacheFlushEnable =
          (flags & (PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH |
-                   PIPE_CONTROL_FLUSH_HDC)) &&
+                   PIPE_CONTROL_FLUSH_HDC |
+                   PIPE_CONTROL_DATA_CACHE_FLUSH)) &&
          IS_COMPUTE_PIPELINE(batch);
       pc.HDCPipelineFlushEnable |= pc.UntypedDataPortCacheFlushEnable;
       pc.CCSFlushEnable |= flags & PIPE_CONTROL_CCS_CACHE_FLUSH;