r600g,radeonsi: consolidate tiling_info initialization

and the util_format_s3tc_init calls too.

src/gallium/drivers/r600/evergreen_state.c

@@ -1195,7 +1195,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 		if (util_format_get_blocksize(pipe_format) >= 16)
 			non_disp_tiling = 1;
 	}
-	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+	nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
 
 	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
 	        height = 1;
@@ -1348,7 +1348,7 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
 	unsigned block_size =
 		align(util_format_get_blocksize(pipe_buffer->format), 4);
 	unsigned pitch_alignment =
-		MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
+		MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
 	unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
 
 	/* XXX: This is copied from evergreen_init_color_surface().  I don't
@@ -1456,7 +1456,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
 		if (util_format_get_blocksize(surf->base.format) >= 16)
 			non_disp_tiling = 1;
 	}
-	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+	nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
 	desc = util_format_description(surf->base.format);
 	for (i = 0; i < 4; i++) {
 		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
@@ -1628,7 +1628,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
 	macro_aspect = eg_macro_tile_aspect(macro_aspect);
 	bankw = eg_bank_wh(bankw);
 	bankh = eg_bank_wh(bankh);
-	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+	nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
 	offset >>= 8;
 
 	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
@@ -3655,7 +3655,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
 	sub_cmd = 0x8;
 	lbpp = util_logbase2(bpp);
 	pitch_tile_max = ((pitch / bpp) >> 3) - 1;
-	nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
+	nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
 
 	if (dst_mode == RADEON_SURF_MODE_LINEAR) {
 		/* T2L */

src/gallium/drivers/r600/r600_pipe.c

@@ -32,7 +32,6 @@
 #include "pipe/p_shader_tokens.h"
 #include "util/u_blitter.h"
 #include "util/u_debug.h"
-#include "util/u_format_s3tc.h"
 #include "util/u_memory.h"
 #include "util/u_simple_shaders.h"
 #include "util/u_upload_mgr.h"
@@ -1048,116 +1047,6 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
 	return rscreen->fences.data[rfence->index] != 0;
 }
 
-static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
-{
-	switch ((tiling_config & 0xe) >> 1) {
-	case 0:
-		rscreen->tiling_info.num_channels = 1;
-		break;
-	case 1:
-		rscreen->tiling_info.num_channels = 2;
-		break;
-	case 2:
-		rscreen->tiling_info.num_channels = 4;
-		break;
-	case 3:
-		rscreen->tiling_info.num_channels = 8;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch ((tiling_config & 0x30) >> 4) {
-	case 0:
-		rscreen->tiling_info.num_banks = 4;
-		break;
-	case 1:
-		rscreen->tiling_info.num_banks = 8;
-		break;
-	default:
-		return -EINVAL;
-
-	}
-	switch ((tiling_config & 0xc0) >> 6) {
-	case 0:
-		rscreen->tiling_info.group_bytes = 256;
-		break;
-	case 1:
-		rscreen->tiling_info.group_bytes = 512;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
-{
-	switch (tiling_config & 0xf) {
-	case 0:
-		rscreen->tiling_info.num_channels = 1;
-		break;
-	case 1:
-		rscreen->tiling_info.num_channels = 2;
-		break;
-	case 2:
-		rscreen->tiling_info.num_channels = 4;
-		break;
-	case 3:
-		rscreen->tiling_info.num_channels = 8;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch ((tiling_config & 0xf0) >> 4) {
-	case 0:
-		rscreen->tiling_info.num_banks = 4;
-		break;
-	case 1:
-		rscreen->tiling_info.num_banks = 8;
-		break;
-	case 2:
-		rscreen->tiling_info.num_banks = 16;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch ((tiling_config & 0xf00) >> 8) {
-	case 0:
-		rscreen->tiling_info.group_bytes = 256;
-		break;
-	case 1:
-		rscreen->tiling_info.group_bytes = 512;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int r600_init_tiling(struct r600_screen *rscreen)
-{
-	uint32_t tiling_config = rscreen->b.info.r600_tiling_config;
-
-	/* set default group bytes, overridden by tiling info ioctl */
-	if (rscreen->b.chip_class <= R700) {
-		rscreen->tiling_info.group_bytes = 256;
-	} else {
-		rscreen->tiling_info.group_bytes = 512;
-	}
-
-	if (!tiling_config)
-		return 0;
-
-	if (rscreen->b.chip_class <= R700) {
-		return r600_interpret_tiling(rscreen, tiling_config);
-	} else {
-		return evergreen_interpret_tiling(rscreen, tiling_config);
-	}
-}
-
 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 {
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
@@ -1224,7 +1113,10 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 	}
 	r600_init_screen_resource_functions(&rscreen->b.b);
 
-	r600_common_screen_init(&rscreen->b, ws);
+	if (!r600_common_screen_init(&rscreen->b, ws)) {
+		FREE(rscreen);
+		return NULL;
+	}
 
 	rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 	if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
@@ -1288,13 +1180,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 	rscreen->has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 			      !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 
-	if (r600_init_tiling(rscreen)) {
-		FREE(rscreen);
-		return NULL;
-	}
-
-	util_format_s3tc_init();
-
 	rscreen->fences.bo = NULL;
 	rscreen->fences.data = NULL;
 	rscreen->fences.next_index = 0;

src/gallium/drivers/r600/r600_pipe.h

@@ -218,19 +218,12 @@ struct r600_pipe_fences {
 #define DBG_SB_DISASM	(1 << 27)
 #define DBG_SB_SAFEMATH	(1 << 28)
 
-struct r600_tiling_info {
-	unsigned num_channels;
-	unsigned num_banks;
-	unsigned group_bytes;
-};
-
 struct r600_screen {
 	struct r600_common_screen	b;
 	bool				has_streamout;
 	bool				has_msaa;
 	bool				has_cp_dma;
 	bool				has_compressed_msaa_texturing;
-	struct r600_tiling_info		tiling_info;
 	struct r600_pipe_fences		fences;
 
 	/*for compute global memory binding, we allocate stuff here, instead of

src/gallium/drivers/r600/r600_texture.c

@@ -29,7 +29,6 @@
 #include "r600d.h"
 
 #include <errno.h>
-#include "util/u_format_s3tc.h"
 #include "util/u_memory.h"
 
 
@@ -372,8 +371,8 @@ void r600_texture_get_cmask_info(struct r600_screen *rscreen,
 	unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
 	unsigned element_bits = 4;
 	unsigned cmask_cache_bits = 1024;
-	unsigned num_pipes = rscreen->tiling_info.num_channels;
-	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+	unsigned num_pipes = rscreen->b.tiling_info.num_channels;
+	unsigned pipe_interleave_bytes = rscreen->b.tiling_info.group_bytes;
 
 	unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
 	unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;

src/gallium/drivers/r600/r600_uvd.c

@@ -156,7 +156,7 @@ static struct radeon_winsys_cs_handle* r600_uvd_set_dtb(struct ruvd_msg *msg, st
 	struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
 
 	msg->body.decode.dt_field_mode = buf->base.interlaced;
-	msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->tiling_info.num_banks));
+	msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.tiling_info.num_banks));
 
 	ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
 

src/gallium/drivers/radeon/r600_pipe_common.c

@@ -26,6 +26,7 @@
 
 #include "r600_pipe_common.h"
 #include "tgsi/tgsi_parse.h"
+#include "util/u_format_s3tc.h"
 
 static const struct debug_named_value common_debug_options[] = {
 	/* logging */
@@ -44,7 +45,119 @@ static const struct debug_named_value common_debug_options[] = {
 	DEBUG_NAMED_VALUE_END /* must be last */
 };
 
-void r600_common_screen_init(struct r600_common_screen *rscreen,
+static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
+				  uint32_t tiling_config)
+{
+	switch ((tiling_config & 0xe) >> 1) {
+	case 0:
+		rscreen->tiling_info.num_channels = 1;
+		break;
+	case 1:
+		rscreen->tiling_info.num_channels = 2;
+		break;
+	case 2:
+		rscreen->tiling_info.num_channels = 4;
+		break;
+	case 3:
+		rscreen->tiling_info.num_channels = 8;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0x30) >> 4) {
+	case 0:
+		rscreen->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		rscreen->tiling_info.num_banks = 8;
+		break;
+	default:
+		return false;
+
+	}
+	switch ((tiling_config & 0xc0) >> 6) {
+	case 0:
+		rscreen->tiling_info.group_bytes = 256;
+		break;
+	case 1:
+		rscreen->tiling_info.group_bytes = 512;
+		break;
+	default:
+		return false;
+	}
+	return true;
+}
+
+static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
+				       uint32_t tiling_config)
+{
+	switch (tiling_config & 0xf) {
+	case 0:
+		rscreen->tiling_info.num_channels = 1;
+		break;
+	case 1:
+		rscreen->tiling_info.num_channels = 2;
+		break;
+	case 2:
+		rscreen->tiling_info.num_channels = 4;
+		break;
+	case 3:
+		rscreen->tiling_info.num_channels = 8;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0xf0) >> 4) {
+	case 0:
+		rscreen->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		rscreen->tiling_info.num_banks = 8;
+		break;
+	case 2:
+		rscreen->tiling_info.num_banks = 16;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0xf00) >> 8) {
+	case 0:
+		rscreen->tiling_info.group_bytes = 256;
+		break;
+	case 1:
+		rscreen->tiling_info.group_bytes = 512;
+		break;
+	default:
+		return false;
+	}
+	return true;
+}
+
+static bool r600_init_tiling(struct r600_common_screen *rscreen)
+{
+	uint32_t tiling_config = rscreen->info.r600_tiling_config;
+
+	/* set default group bytes, overridden by tiling info ioctl */
+	if (rscreen->chip_class <= R700) {
+		rscreen->tiling_info.group_bytes = 256;
+	} else {
+		rscreen->tiling_info.group_bytes = 512;
+	}
+
+	if (!tiling_config)
+		return true;
+
+	if (rscreen->chip_class <= R700) {
+		return r600_interpret_tiling(rscreen, tiling_config);
+	} else {
+		return evergreen_interpret_tiling(rscreen, tiling_config);
+	}
+}
+
+bool r600_common_screen_init(struct r600_common_screen *rscreen,
 			     struct radeon_winsys *ws)
 {
 	ws->query_info(ws, &rscreen->info);
@@ -54,9 +167,16 @@ void r600_common_screen_init(struct r600_common_screen *rscreen,
 	rscreen->chip_class = rscreen->info.chip_class;
 	rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 
+	if (!r600_init_tiling(rscreen)) {
+		return false;
+	}
+
+	util_format_s3tc_init();
+
 	/* Create the auxiliary context. */
 	pipe_mutex_init(rscreen->aux_context_lock);
 	rscreen->aux_context = rscreen->b.context_create(&rscreen->b, NULL);
+	return true;
 }
 
 void r600_common_screen_cleanup(struct r600_common_screen *rscreen)

src/gallium/drivers/radeon/r600_pipe_common.h

@@ -144,12 +144,19 @@ struct r600_texture {
 	unsigned			mipmap_shift;
 };
 
+struct r600_tiling_info {
+	unsigned num_channels;
+	unsigned num_banks;
+	unsigned group_bytes;
+};
+
 struct r600_common_screen {
 	struct pipe_screen		b;
 	struct radeon_winsys		*ws;
 	enum radeon_family		family;
 	enum chip_class			chip_class;
 	struct radeon_info		info;
+	struct r600_tiling_info		tiling_info;
 	unsigned			debug_flags;
 
 	/* Auxiliary context. Mainly used to initialize resources.
@@ -239,7 +246,7 @@ struct r600_common_context {
 };
 
 /* r600_common_pipe.c */
-void r600_common_screen_init(struct r600_common_screen *rscreen,
+bool r600_common_screen_init(struct r600_common_screen *rscreen,
 			     struct radeon_winsys *ws);
 void r600_common_screen_cleanup(struct r600_common_screen *rscreen);
 bool r600_common_context_init(struct r600_common_context *rctx,

src/gallium/drivers/radeonsi/r600.h

@@ -37,12 +37,6 @@
 
 struct winsys_handle;
 
-struct r600_tiling_info {
-	unsigned num_channels;
-	unsigned num_banks;
-	unsigned group_bytes;
-};
-
 /* R600/R700 STATES */
 struct r600_query {
 	union {

src/gallium/drivers/radeonsi/r600_texture.c

@@ -27,7 +27,6 @@
 #include <errno.h>
 #include "pipe/p_screen.h"
 #include "util/u_format.h"
-#include "util/u_format_s3tc.h"
 #include "util/u_math.h"
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
@@ -352,8 +351,8 @@ static void si_texture_get_cmask_info(struct r600_screen *rscreen,
 				      struct r600_texture *rtex,
 				      struct r600_cmask_info *out)
 {
-	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
-	unsigned num_pipes = rscreen->tiling_info.num_channels;
+	unsigned pipe_interleave_bytes = rscreen->b.tiling_info.group_bytes;
+	unsigned num_pipes = rscreen->b.tiling_info.num_channels;
 	unsigned cl_width, cl_height;
 
 	switch (num_pipes) {

src/gallium/drivers/radeonsi/radeonsi_pipe.c

@@ -31,7 +31,6 @@
 #include "util/u_blitter.h"
 #include "util/u_double_list.h"
 #include "util/u_format.h"
-#include "util/u_format_s3tc.h"
 #include "util/u_transfer.h"
 #include "util/u_surface.h"
 #include "util/u_pack_color.h"
@@ -751,65 +750,6 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
 	return rscreen->fences.data[rfence->index] != 0;
 }
 
-static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
-{
-	switch (tiling_config & 0xf) {
-	case 0:
-		rscreen->tiling_info.num_channels = 1;
-		break;
-	case 1:
-		rscreen->tiling_info.num_channels = 2;
-		break;
-	case 2:
-		rscreen->tiling_info.num_channels = 4;
-		break;
-	case 3:
-		rscreen->tiling_info.num_channels = 8;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch ((tiling_config & 0xf0) >> 4) {
-	case 0:
-		rscreen->tiling_info.num_banks = 4;
-		break;
-	case 1:
-		rscreen->tiling_info.num_banks = 8;
-		break;
-	case 2:
-		rscreen->tiling_info.num_banks = 16;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	switch ((tiling_config & 0xf00) >> 8) {
-	case 0:
-		rscreen->tiling_info.group_bytes = 256;
-		break;
-	case 1:
-		rscreen->tiling_info.group_bytes = 512;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int r600_init_tiling(struct r600_screen *rscreen)
-{
-	uint32_t tiling_config = rscreen->b.info.r600_tiling_config;
-
-	/* set default group bytes, overridden by tiling info ioctl */
-	rscreen->tiling_info.group_bytes = 512;
-
-	if (!tiling_config)
-		return 0;
-
-	return evergreen_interpret_tiling(rscreen, tiling_config);
-}
-
 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 {
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
@@ -848,20 +788,16 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 	}
 	r600_init_screen_resource_functions(&rscreen->b.b);
 
-	r600_common_screen_init(&rscreen->b, ws);
+	if (!r600_common_screen_init(&rscreen->b, ws)) {
+		FREE(rscreen);
+		return NULL;
+	}
 
 	if (debug_get_bool_option("RADEON_PRINT_TEXDEPTH", FALSE))
 		rscreen->b.debug_flags |= DBG_TEX_DEPTH;
 	if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 		rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 
-	if (r600_init_tiling(rscreen)) {
-		FREE(rscreen);
-		return NULL;
-	}
-
-	util_format_s3tc_init();
-
 	rscreen->fences.bo = NULL;
 	rscreen->fences.data = NULL;
 	rscreen->fences.next_index = 0;

src/gallium/drivers/radeonsi/radeonsi_pipe.h

@@ -66,8 +66,6 @@ struct r600_pipe_fences {
 
 struct r600_screen {
 	struct r600_common_screen	b;
-	struct r600_tiling_info		tiling_info;
-	struct util_slab_mempool	pool_buffers;
 	struct r600_pipe_fences		fences;
 #if R600_TRACE_CS
 	struct r600_resource		*trace_bo;

src/gallium/drivers/radeonsi/si_state.c

@@ -1762,7 +1762,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
 		macro_aspect = cik_macro_tile_aspect(macro_aspect);
 		bankw = cik_bank_wh(bankw);
 		bankh = cik_bank_wh(bankh);
-		nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
+		nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
 		pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
 						 rscreen->b.info.r600_num_backends);