asahi: remove unstable uapi header
now unused. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Eric Engestrom <eric@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33984>
This commit is contained in:
Alyssa Rosenzweig
committed by
Marge Bot
Marge Bot
parent
c64a2bbff5
commit
1a76310fb7
@@ -1,888 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) The Asahi Linux Contributors
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*
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* Based on panfrost_drm.h which is
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*
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* Copyright © 2014-2018 Broadcom
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* Copyright © 2019 Collabora ltd.
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*/
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/* clang-format off */
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#ifndef _ASAHI_DRM_H_
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#define _ASAHI_DRM_H_
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#include "drm-uapi/drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*
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* The UAPI defined in this file MUST NOT BE USED. End users, DO NOT attempt to
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* use upstream Mesa with asahi kernels, it will blow up. Distro packagers, DO
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* NOT patch upstream Mesa to do the same.
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*/
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#define DRM_ASAHI_UNSTABLE_UABI_VERSION (0xDEADBEEF)
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#define DRM_ASAHI_GET_PARAMS 0x00
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#define DRM_ASAHI_VM_CREATE 0x01
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#define DRM_ASAHI_VM_DESTROY 0x02
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#define DRM_ASAHI_GEM_CREATE 0x03
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#define DRM_ASAHI_GEM_MMAP_OFFSET 0x04
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#define DRM_ASAHI_GEM_BIND 0x05
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#define DRM_ASAHI_QUEUE_CREATE 0x06
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#define DRM_ASAHI_QUEUE_DESTROY 0x07
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#define DRM_ASAHI_SUBMIT 0x08
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#define DRM_ASAHI_GET_TIME 0x09
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/* TODO: Maybe merge with DRM_ASAHI_GEM_BIND? (Becomes IOWR) */
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#define DRM_ASAHI_GEM_BIND_OBJECT 0x0a
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/* TODO: Bump to 64, just in case? */
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#define DRM_ASAHI_MAX_CLUSTERS 32
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struct drm_asahi_params_global {
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__u32 unstable_uabi_version;
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__u32 pad0;
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/** @feat_compat: Compatible feature bits, from drm_asahi_feat_compat */
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__u64 feat_compat;
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/** @feat_incompat: Incompatible feature bits, from drm_asahi_feat_incompat */
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__u64 feat_incompat;
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/** @gpu_generation: GPU generation, e.g. 13 for G13G */
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__u32 gpu_generation;
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/** @gpu_variant: GPU variant as a character, e.g. 'G' for G13G */
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__u32 gpu_variant;
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/** @gpu_revision: GPU revision in BCD, e.g. 0x00 for 'A0', 0x21 for 'C1' */
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__u32 gpu_revision;
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/** @chip_id: Chip ID in BCD, e.g. 0x8103 for T8103 */
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__u32 chip_id;
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/** @num_dies: Number of dies in the SoC */
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__u32 num_dies;
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/** @num_clusters_total: Number of GPU clusters (across all dies) */
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__u32 num_clusters_total;
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/** @num_cores_per_cluster: Number of logical cores per cluster
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* (including inactive/nonexistent) */
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__u32 num_cores_per_cluster;
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/** @num_frags_per_cluster: Number of frags per cluster */
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__u32 num_frags_per_cluster;
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/** @num_gps_per_cluster: Number of GPs per cluster */
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__u32 num_gps_per_cluster;
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/** @num_cores_total_active: Total number of active cores (total bit weight of core_masks) */
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__u32 num_cores_total_active;
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/** @core_masks: Bitmask of present/enabled cores per cluster */
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__u64 core_masks[DRM_ASAHI_MAX_CLUSTERS];
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/** @vm_page_size: GPU VM page size */
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__u32 vm_page_size;
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/** @pad1: Padding, MBZ */
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__u32 pad1;
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/** @vm_user_start: VM user range start VMA */
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__u64 vm_user_start;
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/** @vm_user_end: VM user range end VMA */
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__u64 vm_user_end;
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/** @vm_usc_start: VM USC region start VMA (zero if flexible) */
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__u64 vm_usc_start;
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/** @vm_usc_end: VM USC region end VMA (zero if flexible) */
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__u64 vm_usc_end;
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/** @vm_kernel_min_size: Minimum kernel VMA window size within user range */
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__u64 vm_kernel_min_size;
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/** @max_syncs_per_submission: Maximum number of supported sync objects per submission */
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__u32 max_syncs_per_submission;
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/** @max_commands_per_submission: Maximum number of supported commands per submission */
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__u32 max_commands_per_submission;
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/** @max_commands_in_flight: Maximum number of commands simultaneously in flight per queue */
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/* TODO: Remove? */
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__u32 max_commands_in_flight;
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/** @max_attachments: Maximum number of attachments per command */
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__u32 max_attachments;
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/** @timer_frequency_hz: Clock frequency for timestamps */
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/* TODO: Switch to u64 */
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__u32 timer_frequency_hz;
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/** @min_frequency_khz: Minimum GPU core clock frequency */
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__u32 min_frequency_khz;
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/** @max_frequency_khz: Maximum GPU core clock frequency */
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__u32 max_frequency_khz;
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/** @max_power_mw: Maximum GPU power consumption */
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__u32 max_power_mw;
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/** @result_render_size: Result structure size for render commands */
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__u32 result_render_size;
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/** @result_compute_size: Result structure size for compute commands */
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__u32 result_compute_size;
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/** @firmware_version: GPU firmware version, as 4 integers */
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/* TODO: Do something to distinguish iOS */
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__u32 firmware_version[4];
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/** @user_timestamp_frequency_hz: Timebase frequency for user timestamps */
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__u64 user_timestamp_frequency_hz;
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};
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/** Compatible feature bits */
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enum drm_asahi_feat_compat {
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/** GPU has soft faults enabled (for USC and texture sampling) */
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DRM_ASAHI_FEAT_SOFT_FAULTS = (1UL) << 0,
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DRM_ASAHI_FEAT_GETTIME = (1UL) << 1, /* Remove for upstream */
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DRM_ASAHI_FEAT_USER_TIMESTAMPS = (1UL) << 2,
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};
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/** Incompatible feature bits */
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enum drm_asahi_feat_incompat {
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/** GPU requires compression for Z/S buffers */
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DRM_ASAHI_FEAT_MANDATORY_ZS_COMPRESSION = (1UL) << 0,
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};
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/** Get driver/GPU parameters */
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struct drm_asahi_get_params {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @param: Parameter group to fetch (MBZ) */
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__u32 param_group;
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/** @pad: MBZ */
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__u32 pad;
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/** @value: User pointer to write parameter struct */
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__u64 pointer;
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/** @value: Size of user buffer, max size supported on return */
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__u64 size;
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};
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/** Create a GPU VM address space */
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struct drm_asahi_vm_create {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @kernel_start: Start of the kernel-reserved address range */
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__u64 kernel_start;
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/** @kernel_end: End of the kernel-reserved address range */
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__u64 kernel_end;
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/** @value: Returned VM ID */
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__u32 vm_id;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** Destroy a GPU VM address space */
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struct drm_asahi_vm_destroy {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @value: VM ID to be destroyed */
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__u32 vm_id;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** BO should be CPU-mapped as writeback, not write-combine (optimize for CPU reads) */
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#define ASAHI_GEM_WRITEBACK (1L << 0)
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/** BO is private to this GPU VM (no exports) */
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#define ASAHI_GEM_VM_PRIVATE (1L << 1)
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/** Destroy a GPU VM address space */
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struct drm_asahi_gem_create {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @size: Size of the BO */
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__u64 size;
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/** @flags: BO creation flags */
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__u32 flags;
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/** @handle: VM ID to assign to the BO, if ASAHI_GEM_VM_PRIVATE is set. */
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__u32 vm_id;
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/** @handle: Returned GEM handle for the BO */
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__u32 handle;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** Get BO mmap offset */
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struct drm_asahi_gem_mmap_offset {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @handle: Handle for the object being mapped. */
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__u32 handle;
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/** @flags: Must be zero */
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__u32 flags;
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/** @offset: The fake offset to use for subsequent mmap call */
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__u64 offset;
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};
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/** VM_BIND operations */
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enum drm_asahi_bind_op {
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/** Bind a BO to a GPU VMA range */
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ASAHI_BIND_OP_BIND = 0,
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/** Unbind a GPU VMA range */
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ASAHI_BIND_OP_UNBIND = 1,
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/** Unbind all mappings of a given BO */
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ASAHI_BIND_OP_UNBIND_ALL = 2,
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};
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/** Map BO with GPU read permission */
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#define ASAHI_BIND_READ (1L << 0)
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/** Map BO with GPU write permission */
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#define ASAHI_BIND_WRITE (1L << 1)
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/** BO VM_BIND operations */
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struct drm_asahi_gem_bind {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @obj: Bind operation (enum drm_asahi_bind_op) */
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__u32 op;
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/** @flags: One or more of ASAHI_BIND_* (BIND only) */
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__u32 flags;
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/** @obj: GEM object to bind/unbind (BIND or UNBIND_ALL) */
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__u32 handle;
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/** @vm_id: The ID of the VM to operate on */
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__u32 vm_id;
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/** @offset: Offset into the object (BIND only) */
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__u64 offset;
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/** @range: Number of bytes to bind/unbind to addr (BIND or UNBIND only) */
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__u64 range;
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/** @addr: Address to bind to (BIND or UNBIND only) */
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__u64 addr;
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};
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/** VM_BIND operations */
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enum drm_asahi_bind_object_op {
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/** Bind a BO as a special GPU object */
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ASAHI_BIND_OBJECT_OP_BIND = 0,
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/** Unbind a special GPU object */
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ASAHI_BIND_OBJECT_OP_UNBIND = 1,
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};
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/** Map a BO as a timestamp buffer */
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#define ASAHI_BIND_OBJECT_USAGE_TIMESTAMPS (1L << 0)
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/** BO special object operations */
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struct drm_asahi_gem_bind_object {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @obj: Bind operation (enum drm_asahi_bind_object_op) */
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__u32 op;
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/** @flags: One or more of ASAHI_BIND_OBJECT_* */
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__u32 flags;
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/** @obj: GEM object to bind/unbind (BIND) */
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__u32 handle;
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/** @vm_id: The ID of the VM to operate on (MBZ currently) */
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__u32 vm_id;
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/** @offset: Offset into the object (BIND only) */
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__u64 offset;
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/** @range: Number of bytes to bind/unbind (BIND only) */
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__u64 range;
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/** @addr: Object handle (out for BIND, in for UNBIND) */
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__u32 object_handle;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** Command type */
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enum drm_asahi_cmd_type {
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/** Render command (Render subqueue, Vert+Frag) */
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DRM_ASAHI_CMD_RENDER = 0,
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/** Blit command (Render subqueue, Frag only, not yet supported) */
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DRM_ASAHI_CMD_BLIT = 1,
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/** Compute command (Compute subqueue) */
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DRM_ASAHI_CMD_COMPUTE = 2,
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};
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/** Queue capabilities */
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/* Note: this is an enum so that it can be resolved by Rust bindgen. */
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enum drm_asahi_queue_cap {
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/** Supports render commands */
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DRM_ASAHI_QUEUE_CAP_RENDER = (1UL << DRM_ASAHI_CMD_RENDER),
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/** Supports blit commands */
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DRM_ASAHI_QUEUE_CAP_BLIT = (1UL << DRM_ASAHI_CMD_BLIT),
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/** Supports compute commands */
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DRM_ASAHI_QUEUE_CAP_COMPUTE = (1UL << DRM_ASAHI_CMD_COMPUTE),
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};
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/** Create a queue */
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struct drm_asahi_queue_create {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @flags: MBZ */
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__u32 flags;
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/** @vm_id: The ID of the VM this queue is bound to */
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__u32 vm_id;
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/** @type: Bitmask of DRM_ASAHI_QUEUE_CAP_* */
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__u32 queue_caps;
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/** @priority: Queue priority, 0-3 */
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__u32 priority;
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/** @queue_id: The returned queue ID */
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__u32 queue_id;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** Destroy a queue */
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struct drm_asahi_queue_destroy {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @queue_id: The queue ID to be destroyed */
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__u32 queue_id;
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/** @pad: MBZ */
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__u32 pad;
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};
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/** Sync item types */
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enum drm_asahi_sync_type {
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/** Simple sync object */
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DRM_ASAHI_SYNC_SYNCOBJ = 0,
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/** Timeline sync object */
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DRM_ASAHI_SYNC_TIMELINE_SYNCOBJ = 1,
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};
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/** Sync item */
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struct drm_asahi_sync {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @sync_type: One of drm_asahi_sync_type */
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__u32 sync_type;
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/** @handle: The sync object handle */
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__u32 handle;
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/** @timeline_value: Timeline value for timeline sync objects */
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__u64 timeline_value;
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};
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/** Sub-queues within a queue */
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enum drm_asahi_subqueue {
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/** Render subqueue (also blit) */
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DRM_ASAHI_SUBQUEUE_RENDER = 0,
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/** Compute subqueue */
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DRM_ASAHI_SUBQUEUE_COMPUTE = 1,
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/** Queue count, must remain multiple of 2 for struct alignment */
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DRM_ASAHI_SUBQUEUE_COUNT = 2,
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};
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/** Command index for no barrier */
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#define DRM_ASAHI_BARRIER_NONE ~(0U)
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/** Top level command structure */
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struct drm_asahi_command {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @type: One of drm_asahi_cmd_type */
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__u32 cmd_type;
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/** @flags: Flags for command submission */
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__u32 flags;
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/** @cmdbuf: Pointer to the appropriate command buffer structure */
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__u64 cmd_buffer;
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/** @cmdbuf: Size of the command buffer structure */
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__u64 cmd_buffer_size;
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/** @cmdbuf: Offset into the result BO to return information about this command */
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__u64 result_offset;
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/** @cmdbuf: Size of the result data structure */
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__u64 result_size;
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/** @barriers: Array of command indices per subqueue to wait on */
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__u32 barriers[DRM_ASAHI_SUBQUEUE_COUNT];
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};
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/** Submit an array of commands to a queue */
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struct drm_asahi_submit {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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/** @in_syncs: An optional array of drm_asahi_sync to wait on before starting this job. */
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__u64 in_syncs;
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/** @in_syncs: An optional array of drm_asahi_sync objects to signal upon completion. */
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__u64 out_syncs;
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/** @commands: Pointer to the drm_asahi_command array of commands to submit. */
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__u64 commands;
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/** @flags: Flags for command submission (MBZ) */
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__u32 flags;
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/** @queue_id: The queue ID to be submitted to */
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__u32 queue_id;
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/** @result_handle: An optional BO handle to place result data in */
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__u32 result_handle;
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/** @in_sync_count: Number of sync objects to wait on before starting this job. */
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__u32 in_sync_count;
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/** @in_sync_count: Number of sync objects to signal upon completion of this job. */
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__u32 out_sync_count;
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/** @pad: Number of commands to be submitted */
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__u32 command_count;
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};
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/** An attachment definition for a shader stage */
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struct drm_asahi_attachment {
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/** @pointer: Base address of the attachment */
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__u64 pointer;
|
||||
/** @size: Size of the attachment in bytes */
|
||||
__u64 size;
|
||||
/** @order: Power of 2 exponent related to attachment size (?) */
|
||||
__u32 order;
|
||||
/** @flags: MBZ */
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/** XXX investigate real meaning */
|
||||
#define ASAHI_RENDER_NO_CLEAR_PIPELINE_TEXTURES (1UL << 0)
|
||||
/** XXX investigate real meaning */
|
||||
#define ASAHI_RENDER_SET_WHEN_RELOADING_Z_OR_S (1UL << 1)
|
||||
/** Vertex stage shader spills */
|
||||
#define ASAHI_RENDER_VERTEX_SPILLS (1UL << 2)
|
||||
/** Process empty tiles through the fragment load/store */
|
||||
#define ASAHI_RENDER_PROCESS_EMPTY_TILES (1UL << 3)
|
||||
/** Run vertex stage on a single cluster (on multicluster GPUs) */
|
||||
#define ASAHI_RENDER_NO_VERTEX_CLUSTERING (1UL << 4)
|
||||
/** Enable MSAA for Z/S */
|
||||
#define ASAHI_RENDER_MSAA_ZS (1UL << 5)
|
||||
/** Disable preemption (XXX check) */
|
||||
#define ASAHI_RENDER_NO_PREEMPTION (1UL << 6)
|
||||
|
||||
/** Render command submission data */
|
||||
struct drm_asahi_cmd_render {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
/** @flags: Zero or more of ASAHI_RENDER_* */
|
||||
__u64 flags;
|
||||
|
||||
__u64 encoder_ptr;
|
||||
__u64 vertex_usc_base;
|
||||
__u64 fragment_usc_base;
|
||||
|
||||
__u64 vertex_attachments;
|
||||
__u64 fragment_attachments;
|
||||
__u32 vertex_attachment_count;
|
||||
__u32 fragment_attachment_count;
|
||||
|
||||
__u32 vertex_helper_program;
|
||||
__u32 fragment_helper_program;
|
||||
__u32 vertex_helper_cfg;
|
||||
__u32 fragment_helper_cfg;
|
||||
__u64 vertex_helper_arg;
|
||||
__u64 fragment_helper_arg;
|
||||
|
||||
__u64 depth_buffer_load;
|
||||
__u64 depth_buffer_load_stride;
|
||||
__u64 depth_buffer_store;
|
||||
__u64 depth_buffer_store_stride;
|
||||
__u64 depth_buffer_partial;
|
||||
__u64 depth_buffer_partial_stride;
|
||||
__u64 depth_meta_buffer_load;
|
||||
__u64 depth_meta_buffer_load_stride;
|
||||
__u64 depth_meta_buffer_store;
|
||||
__u64 depth_meta_buffer_store_stride;
|
||||
__u64 depth_meta_buffer_partial;
|
||||
__u64 depth_meta_buffer_partial_stride;
|
||||
|
||||
__u64 stencil_buffer_load;
|
||||
__u64 stencil_buffer_load_stride;
|
||||
__u64 stencil_buffer_store;
|
||||
__u64 stencil_buffer_store_stride;
|
||||
__u64 stencil_buffer_partial;
|
||||
__u64 stencil_buffer_partial_stride;
|
||||
__u64 stencil_meta_buffer_load;
|
||||
__u64 stencil_meta_buffer_load_stride;
|
||||
__u64 stencil_meta_buffer_store;
|
||||
__u64 stencil_meta_buffer_store_stride;
|
||||
__u64 stencil_meta_buffer_partial;
|
||||
__u64 stencil_meta_buffer_partial_stride;
|
||||
|
||||
__u64 scissor_array;
|
||||
__u64 depth_bias_array;
|
||||
__u64 visibility_result_buffer;
|
||||
|
||||
__u64 vertex_sampler_array;
|
||||
__u32 vertex_sampler_count;
|
||||
__u32 vertex_sampler_max;
|
||||
|
||||
__u64 fragment_sampler_array;
|
||||
__u32 fragment_sampler_count;
|
||||
__u32 fragment_sampler_max;
|
||||
|
||||
__u64 zls_ctrl;
|
||||
__u64 ppp_multisamplectl;
|
||||
__u32 ppp_ctrl;
|
||||
|
||||
__u32 fb_width;
|
||||
__u32 fb_height;
|
||||
|
||||
__u32 utile_width;
|
||||
__u32 utile_height;
|
||||
|
||||
__u32 samples;
|
||||
__u32 layers;
|
||||
|
||||
__u32 encoder_id;
|
||||
__u32 cmd_ta_id;
|
||||
__u32 cmd_3d_id;
|
||||
|
||||
__u32 sample_size;
|
||||
__u32 tib_blocks;
|
||||
__u32 iogpu_unk_214;
|
||||
|
||||
__u32 merge_upper_x;
|
||||
__u32 merge_upper_y;
|
||||
|
||||
__u32 load_pipeline;
|
||||
__u32 load_pipeline_bind;
|
||||
|
||||
__u32 store_pipeline;
|
||||
__u32 store_pipeline_bind;
|
||||
|
||||
__u32 partial_reload_pipeline;
|
||||
__u32 partial_reload_pipeline_bind;
|
||||
|
||||
__u32 partial_store_pipeline;
|
||||
__u32 partial_store_pipeline_bind;
|
||||
|
||||
__u32 depth_dimensions;
|
||||
__u32 isp_bgobjdepth;
|
||||
__u32 isp_bgobjvals;
|
||||
};
|
||||
|
||||
#define ASAHI_RENDER_UNK_UNK1 (1UL << 0)
|
||||
#define ASAHI_RENDER_UNK_SET_TILE_CONFIG (1UL << 1)
|
||||
#define ASAHI_RENDER_UNK_SET_UTILE_CONFIG (1UL << 2)
|
||||
#define ASAHI_RENDER_UNK_SET_AUX_FB_UNK (1UL << 3)
|
||||
#define ASAHI_RENDER_UNK_SET_G14_UNK (1UL << 4)
|
||||
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_UNK_140 (1UL << 20)
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_UNK_158 (1UL << 21)
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_TILECFG (1UL << 22)
|
||||
#define ASAHI_RENDER_UNK_SET_LOAD_BGOBJVALS (1UL << 23)
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_UNK_38 (1UL << 24)
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_UNK_3C (1UL << 25)
|
||||
|
||||
#define ASAHI_RENDER_UNK_SET_RELOAD_ZLSCTRL (1UL << 27)
|
||||
#define ASAHI_RENDER_UNK_SET_UNK_BUF_10 (1UL << 28)
|
||||
#define ASAHI_RENDER_UNK_SET_FRG_UNK_MASK (1UL << 29)
|
||||
|
||||
#define ASAHI_RENDER_UNK_SET_IOGPU_UNK54 (1UL << 40)
|
||||
#define ASAHI_RENDER_UNK_SET_IOGPU_UNK56 (1UL << 41)
|
||||
#define ASAHI_RENDER_UNK_SET_TILING_CONTROL (1UL << 42)
|
||||
#define ASAHI_RENDER_UNK_SET_TILING_CONTROL_2 (1UL << 43)
|
||||
#define ASAHI_RENDER_UNK_SET_VTX_UNK_F0 (1UL << 44)
|
||||
#define ASAHI_RENDER_UNK_SET_VTX_UNK_F8 (1UL << 45)
|
||||
#define ASAHI_RENDER_UNK_SET_VTX_UNK_118 (1UL << 46)
|
||||
#define ASAHI_RENDER_UNK_SET_VTX_UNK_MASK (1UL << 47)
|
||||
|
||||
#define ASAHI_RENDER_EXT_UNKNOWNS 0xff00
|
||||
|
||||
/* XXX: Do not upstream this struct */
|
||||
struct drm_asahi_cmd_render_unknowns {
|
||||
/** @type: Type ID of this extension */
|
||||
__u32 type;
|
||||
__u32 pad;
|
||||
/** @next: Pointer to the next extension struct, if any */
|
||||
__u64 next;
|
||||
|
||||
__u64 flags;
|
||||
|
||||
__u64 tile_config;
|
||||
__u64 utile_config;
|
||||
|
||||
__u64 aux_fb_unk;
|
||||
__u64 g14_unk;
|
||||
__u64 frg_unk_140;
|
||||
__u64 frg_unk_158;
|
||||
__u64 frg_tilecfg;
|
||||
__u64 load_bgobjvals;
|
||||
__u64 frg_unk_38;
|
||||
__u64 frg_unk_3c;
|
||||
__u64 reload_zlsctrl;
|
||||
__u64 unk_buf_10;
|
||||
__u64 frg_unk_mask;
|
||||
|
||||
__u64 iogpu_unk54;
|
||||
__u64 iogpu_unk56;
|
||||
__u64 tiling_control;
|
||||
__u64 tiling_control_2;
|
||||
__u64 vtx_unk_f0;
|
||||
__u64 vtx_unk_f8;
|
||||
__u64 vtx_unk_118;
|
||||
__u64 vtx_unk_mask;
|
||||
};
|
||||
|
||||
#define ASAHI_RENDER_EXT_TIMESTAMPS 0x0001
|
||||
|
||||
/** User timestamp buffers for render commands */
|
||||
struct drm_asahi_cmd_render_user_timestamps {
|
||||
/** @type: Type ID of this extension */
|
||||
__u32 type;
|
||||
/** @pad: MBZ */
|
||||
__u32 pad;
|
||||
/** @next: Pointer to the next extension struct, if any */
|
||||
__u64 next;
|
||||
|
||||
/** @vtx_start_handle: Handle of the timestamp buffer for the vertex start ts */
|
||||
__u32 vtx_start_handle;
|
||||
/** @vtx_start_offset: Offset into the timestamp buffer of the vertex start ts */
|
||||
__u32 vtx_start_offset;
|
||||
|
||||
/** @vtx_end_handle: Handle of the timestamp buffer for the vertex end ts */
|
||||
__u32 vtx_end_handle;
|
||||
/** @vtx_end_offset: Offset into the timestamp buffer of the vertex end ts */
|
||||
__u32 vtx_end_offset;
|
||||
|
||||
/** @frg_start_handle: Handle of the timestamp buffer for the fragment start ts */
|
||||
__u32 frg_start_handle;
|
||||
/** @frg_start_offset: Offset into the timestamp buffer of the fragment start ts */
|
||||
__u32 frg_start_offset;
|
||||
|
||||
/** @frg_end_handle: Handle of the timestamp buffer for the fragment end ts */
|
||||
__u32 frg_end_handle;
|
||||
/** @frg_end_offset: Offset into the timestamp buffer of the fragment end ts */
|
||||
__u32 frg_end_offset;
|
||||
};
|
||||
|
||||
/* XXX check */
|
||||
#define ASAHI_COMPUTE_NO_PREEMPTION (1UL << 0)
|
||||
|
||||
/** Compute command submission data */
|
||||
struct drm_asahi_cmd_compute {
|
||||
/* TODO: remove guards on next bump */
|
||||
#if DRM_ASAHI_UNSTABLE_UABI_VERSION > 10011
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
#endif
|
||||
|
||||
__u64 flags;
|
||||
|
||||
__u64 encoder_ptr;
|
||||
__u64 encoder_end;
|
||||
__u64 usc_base;
|
||||
|
||||
__u64 attachments;
|
||||
__u32 attachment_count;
|
||||
__u32 pad;
|
||||
|
||||
__u32 helper_program;
|
||||
__u32 helper_cfg;
|
||||
__u64 helper_arg;
|
||||
|
||||
__u32 encoder_id;
|
||||
__u32 cmd_id;
|
||||
|
||||
__u64 sampler_array;
|
||||
__u32 sampler_count;
|
||||
__u32 sampler_max;
|
||||
|
||||
__u32 iogpu_unk_40;
|
||||
__u32 unk_mask;
|
||||
|
||||
#if DRM_ASAHI_UNSTABLE_UABI_VERSION <= 10011
|
||||
/* We forgot the extension pointer in <=10011... */
|
||||
__u64 extensions;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define ASAHI_COMPUTE_EXT_TIMESTAMPS 0x0001
|
||||
|
||||
/** User timestamp buffers for compute commands */
|
||||
struct drm_asahi_cmd_compute_user_timestamps {
|
||||
/** @type: Type ID of this extension */
|
||||
__u32 type;
|
||||
/** @pad: MBZ */
|
||||
__u32 pad;
|
||||
/** @next: Pointer to the next extension struct, if any */
|
||||
__u64 next;
|
||||
|
||||
/** @start_handle: Handle of the timestamp buffer for the start ts */
|
||||
__u32 start_handle;
|
||||
/** @start_offset: Offset into the timestamp buffer of the start ts */
|
||||
__u32 start_offset;
|
||||
|
||||
/** @end_handle: Handle of the timestamp buffer for the end ts */
|
||||
__u32 end_handle;
|
||||
/** @end_offset: Offset into the timestamp buffer of the end ts */
|
||||
__u32 end_offset;
|
||||
|
||||
};
|
||||
|
||||
/** Command completion status */
|
||||
enum drm_asahi_status {
|
||||
DRM_ASAHI_STATUS_PENDING = 0,
|
||||
DRM_ASAHI_STATUS_COMPLETE,
|
||||
DRM_ASAHI_STATUS_UNKNOWN_ERROR,
|
||||
DRM_ASAHI_STATUS_TIMEOUT,
|
||||
DRM_ASAHI_STATUS_FAULT,
|
||||
DRM_ASAHI_STATUS_KILLED,
|
||||
DRM_ASAHI_STATUS_NO_DEVICE,
|
||||
DRM_ASAHI_STATUS_CHANNEL_ERROR,
|
||||
};
|
||||
|
||||
/** GPU fault information */
|
||||
enum drm_asahi_fault {
|
||||
DRM_ASAHI_FAULT_NONE = 0,
|
||||
DRM_ASAHI_FAULT_UNKNOWN,
|
||||
DRM_ASAHI_FAULT_UNMAPPED,
|
||||
DRM_ASAHI_FAULT_AF_FAULT,
|
||||
DRM_ASAHI_FAULT_WRITE_ONLY,
|
||||
DRM_ASAHI_FAULT_READ_ONLY,
|
||||
DRM_ASAHI_FAULT_NO_ACCESS,
|
||||
};
|
||||
|
||||
/** Common command completion result information */
|
||||
struct drm_asahi_result_info {
|
||||
/** @status: One of enum drm_asahi_status */
|
||||
__u32 status;
|
||||
|
||||
/** @reason: One of drm_asahi_fault_type */
|
||||
__u32 fault_type;
|
||||
|
||||
/** @unit: Unit number, hardware dependent */
|
||||
__u32 unit;
|
||||
|
||||
/** @sideband: Sideband information, hardware dependent */
|
||||
__u32 sideband;
|
||||
|
||||
/** @level: Page table level at which the fault occurred, hardware dependent */
|
||||
__u8 level;
|
||||
|
||||
/** @read: Fault was a read */
|
||||
__u8 is_read;
|
||||
|
||||
/** @pad: MBZ */
|
||||
__u16 pad;
|
||||
|
||||
/** @unk_5: Extra bits, hardware dependent */
|
||||
__u32 extra;
|
||||
|
||||
/** @address: Fault address, cache line aligned */
|
||||
__u64 address;
|
||||
};
|
||||
|
||||
#define DRM_ASAHI_RESULT_RENDER_TVB_GROW_OVF (1UL << 0)
|
||||
#define DRM_ASAHI_RESULT_RENDER_TVB_GROW_MIN (1UL << 1)
|
||||
#define DRM_ASAHI_RESULT_RENDER_TVB_OVERFLOWED (1UL << 2)
|
||||
|
||||
/** Render command completion result information */
|
||||
struct drm_asahi_result_render {
|
||||
/** @address: Common result information */
|
||||
struct drm_asahi_result_info info;
|
||||
|
||||
/** @flags: Zero or more of of DRM_ASAHI_RESULT_RENDER_* */
|
||||
__u64 flags;
|
||||
|
||||
/** @vertex_ts_start: Timestamp of the start of vertex processing */
|
||||
__u64 vertex_ts_start;
|
||||
|
||||
/** @vertex_ts_end: Timestamp of the end of vertex processing */
|
||||
__u64 vertex_ts_end;
|
||||
|
||||
/** @fragment_ts_start: Timestamp of the start of fragment processing */
|
||||
__u64 fragment_ts_start;
|
||||
|
||||
/** @fragment_ts_end: Timestamp of the end of fragment processing */
|
||||
__u64 fragment_ts_end;
|
||||
|
||||
/** @tvb_size_bytes: TVB size at the start of this render */
|
||||
__u64 tvb_size_bytes;
|
||||
|
||||
/** @tvb_usage_bytes: Total TVB usage in bytes for this render */
|
||||
__u64 tvb_usage_bytes;
|
||||
|
||||
/** @num_tvb_overflows: Number of TVB overflows that occurred for this render */
|
||||
__u32 num_tvb_overflows;
|
||||
|
||||
/** @pad: MBZ */
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/** Compute command completion result information */
|
||||
struct drm_asahi_result_compute {
|
||||
/** @address: Common result information */
|
||||
struct drm_asahi_result_info info;
|
||||
|
||||
/** @flags: Zero or more of of DRM_ASAHI_RESULT_COMPUTE_* */
|
||||
__u64 flags;
|
||||
|
||||
/** @ts_start: Timestamp of the start of this compute command */
|
||||
__u64 ts_start;
|
||||
|
||||
/** @vertex_ts_end: Timestamp of the end of this compute command */
|
||||
__u64 ts_end;
|
||||
};
|
||||
|
||||
/** Fetch the current GPU timestamp time */
|
||||
struct drm_asahi_get_time {
|
||||
/** @extensions: Pointer to the first extension struct, if any */
|
||||
__u64 extensions;
|
||||
|
||||
/** @flags: MBZ. */
|
||||
__u64 flags;
|
||||
|
||||
/** @gpu_timestamp: On return, the current GPU timestamp */
|
||||
__u64 gpu_timestamp;
|
||||
};
|
||||
|
||||
/* Note: this is an enum so that it can be resolved by Rust bindgen. */
|
||||
enum {
|
||||
DRM_IOCTL_ASAHI_GET_PARAMS = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_GET_PARAMS, struct drm_asahi_get_params),
|
||||
DRM_IOCTL_ASAHI_VM_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_VM_CREATE, struct drm_asahi_vm_create),
|
||||
DRM_IOCTL_ASAHI_VM_DESTROY = DRM_IOW(DRM_COMMAND_BASE + DRM_ASAHI_VM_DESTROY, struct drm_asahi_vm_destroy),
|
||||
DRM_IOCTL_ASAHI_GEM_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_GEM_CREATE, struct drm_asahi_gem_create),
|
||||
DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_GEM_MMAP_OFFSET, struct drm_asahi_gem_mmap_offset),
|
||||
DRM_IOCTL_ASAHI_GEM_BIND = DRM_IOW(DRM_COMMAND_BASE + DRM_ASAHI_GEM_BIND, struct drm_asahi_gem_bind),
|
||||
DRM_IOCTL_ASAHI_QUEUE_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_QUEUE_CREATE, struct drm_asahi_queue_create),
|
||||
DRM_IOCTL_ASAHI_QUEUE_DESTROY = DRM_IOW(DRM_COMMAND_BASE + DRM_ASAHI_QUEUE_DESTROY, struct drm_asahi_queue_destroy),
|
||||
DRM_IOCTL_ASAHI_SUBMIT = DRM_IOW(DRM_COMMAND_BASE + DRM_ASAHI_SUBMIT, struct drm_asahi_submit),
|
||||
DRM_IOCTL_ASAHI_GET_TIME = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_GET_TIME, struct drm_asahi_get_time),
|
||||
DRM_IOCTL_ASAHI_GEM_BIND_OBJECT = DRM_IOWR(DRM_COMMAND_BASE + DRM_ASAHI_GEM_BIND_OBJECT, struct drm_asahi_gem_bind_object),
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ASAHI_DRM_H_ */
|
||||
Reference in New Issue
Block a user