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nvc0/ir: fix converting between predicate and gpr

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The spill logic will insert convert ops when moving between files. It
seems like the emission logic wasn't quite ready for these converts.

Tested on fermi, and visually looked at nvdisasm output for maxwell.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
This commit is contained in:
Ilia Mirkin
2016-02-04 22:58:48 -05:00
parent 2fed18b8a5
commit 1a0fde1f52
3 changed files with 41 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+7 -1
View File
@@ -1947,10 +1947,16 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
case OP_CEIL:
case OP_FLOOR:
case OP_TRUNC:
case OP_CVT:
case OP_SAT:
emitCVT(insn);
break;
case OP_CVT:
if (insn->def(0).getFile() == FILE_PREDICATE ||
insn->src(0).getFile() == FILE_PREDICATE)
emitMOV(insn);
else
emitCVT(insn);
break;
case OP_RSQ:
emitSFnOp(insn, 5 + 2 * insn->subOp);
break;
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+27 -9
View File
@@ -673,7 +673,12 @@ CodeEmitterGM107::emitMOV()
(insn->sType != TYPE_F32 && !longIMMD(insn->src(0)))) {
switch (insn->src(0).getFile()) {
case FILE_GPR:
emitInsn(0x5c980000);
if (insn->def(0).getFile() == FILE_PREDICATE) {
emitInsn(0x5b6a0000);
emitGPR (0x08);
} else {
emitInsn(0x5c980000);
}
emitGPR (0x14, insn->src(0));
break;
case FILE_MEMORY_CONST:
@@ -684,18 +689,32 @@ CodeEmitterGM107::emitMOV()
emitInsn(0x38980000);
emitIMMD(0x14, 19, insn->src(0));
break;
case FILE_PREDICATE:
emitInsn(0x50880000);
emitPRED(0x0c, insn->src(0));
emitPRED(0x1d);
emitPRED(0x27);
break;
default:
assert(!"bad src file");
break;
}
emitField(0x27, 4, insn->lanes);
if (insn->def(0).getFile() != FILE_PREDICATE &&
insn->src(0).getFile() != FILE_PREDICATE)
emitField(0x27, 4, insn->lanes);
} else {
emitInsn (0x01000000);
emitIMMD (0x14, 32, insn->src(0));
emitField(0x0c, 4, insn->lanes);
}
emitGPR(0x00, insn->def(0));
if (insn->def(0).getFile() == FILE_PREDICATE) {
emitPRED(0x27);
emitPRED(0x03, insn->def(0));
emitPRED(0x00);
} else {
emitGPR(0x00, insn->def(0));
}
}
void
@@ -2684,11 +2703,7 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
emitRAM();
break;
case OP_MOV:
if (insn->def(0).getFile() == FILE_GPR &&
insn->src(0).getFile() != FILE_PREDICATE)
emitMOV();
else
assert(!"R2P/P2R");
emitMOV();
break;
case OP_RDSV:
emitS2R();
@@ -2700,7 +2715,10 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
case OP_CEIL:
case OP_TRUNC:
case OP_CVT:
if (isFloatType(insn->dType)) {
if (insn->op == OP_CVT && (insn->def(0).getFile() == FILE_PREDICATE ||
insn->src(0).getFile() == FILE_PREDICATE)) {
emitMOV();
} else if (isFloatType(insn->dType)) {
if (isFloatType(insn->sType))
emitF2F();
else
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+7 -1
View File
@@ -2435,10 +2435,16 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
case OP_CEIL:
case OP_FLOOR:
case OP_TRUNC:
case OP_CVT:
case OP_SAT:
emitCVT(insn);
break;
case OP_CVT:
if (insn->def(0).getFile() == FILE_PREDICATE ||
insn->src(0).getFile() == FILE_PREDICATE)
emitMOV(insn);
else
emitCVT(insn);
break;
case OP_RSQ:
emitSFnOp(insn, 5 + 2 * insn->subOp);
break;