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asahi: Implement the stencil test

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
This commit is contained in:
Alyssa Rosenzweig
2021-07-05 16:01:13 -04:00
committed by Marge Bot
parent dc968a9bec
commit 18a34dc47e
2 changed files with 43 additions and 6 deletions
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src/asahi/lib/cmdbuf.xml
+4 -4
View File
@@ -271,18 +271,18 @@
</struct>
<struct name="Rasterizer face" size="8">
<field name="Stencil reference" size="8" start="0:0" type="hex" default="0x00"/>
<field name="Stencil reference" size="8" start="0:0" type="hex"/>
<!-- line width is 4:4 fixed point with off-by-one applied -->
<field name="Line width" size="8" start="0:8" type="hex"/>
<field name="Polygon mode" size="2" start="0:18" type="Polygon Mode"/>
<field name="Disable depth write" size="1" start="0:21" type="bool"/>
<field name="Depth function" size="3" start="0:24" type="ZS Func"/>
<field name="Stencil write mask" size="8" start="1:0" type="hex" default="0xFF"/>
<field name="Stencil read mask" size="8" start="1:8" type="hex" default="0xFF"/>
<field name="Stencil write mask" size="8" start="1:0" type="hex"/>
<field name="Stencil read mask" size="8" start="1:8" type="hex"/>
<field name="Depth pass" size="3" start="1:16" type="Stencil Op"/>
<field name="Depth fail" size="3" start="1:19" type="Stencil Op"/>
<field name="Stencil fail" size="3" start="1:22" type="Stencil Op"/>
<field name="Stencil compare" size="3" start="1:25" type="ZS Func" default="Always"/>
<field name="Stencil compare" size="3" start="1:25" type="ZS Func"/>
</struct>
<struct name="Rasterizer" size="28">
src/gallium/drivers/asahi/agx_state.c
+39 -2
View File
@@ -170,14 +170,46 @@ agx_bind_blend_state(struct pipe_context *pctx, void *cso)
ctx->blend = cso;
}
static const enum agx_stencil_op agx_stencil_ops[PIPE_STENCIL_OP_INVERT + 1] = {
[PIPE_STENCIL_OP_KEEP] = AGX_STENCIL_OP_KEEP,
[PIPE_STENCIL_OP_ZERO] = AGX_STENCIL_OP_ZERO,
[PIPE_STENCIL_OP_REPLACE] = AGX_STENCIL_OP_REPLACE,
[PIPE_STENCIL_OP_INCR] = AGX_STENCIL_OP_INCR_SAT,
[PIPE_STENCIL_OP_DECR] = AGX_STENCIL_OP_DECR_SAT,
[PIPE_STENCIL_OP_INCR_WRAP] = AGX_STENCIL_OP_INCR_WRAP,
[PIPE_STENCIL_OP_DECR_WRAP] = AGX_STENCIL_OP_DECR_WRAP,
[PIPE_STENCIL_OP_INVERT] = AGX_STENCIL_OP_INVERT,
};
static void
agx_pack_rasterizer_face(struct agx_rasterizer_face_packed *out,
struct pipe_stencil_state st,
enum agx_zs_func z_func,
bool disable_z_write)
{
agx_pack(out, RASTERIZER_FACE, cfg) {
cfg.depth_function = z_func;
cfg.disable_depth_write = disable_z_write;
if (st.enabled) {
cfg.stencil_write_mask = st.writemask;
cfg.stencil_read_mask = st.valuemask;
cfg.depth_pass = agx_stencil_ops[st.zpass_op];
cfg.depth_fail = agx_stencil_ops[st.zfail_op];
cfg.stencil_fail = agx_stencil_ops[st.fail_op];
cfg.stencil_compare = (enum agx_zs_func) st.func;
} else {
cfg.stencil_write_mask = 0xFF;
cfg.stencil_read_mask = 0xFF;
cfg.depth_pass = AGX_STENCIL_OP_KEEP;
cfg.depth_fail = AGX_STENCIL_OP_KEEP;
cfg.stencil_fail = AGX_STENCIL_OP_KEEP;
cfg.stencil_compare = AGX_ZS_FUNC_ALWAYS;
}
}
}
@@ -204,11 +236,11 @@ agx_create_zsa_state(struct pipe_context *ctx,
((enum agx_zs_func) state->depth_func) : AGX_ZS_FUNC_ALWAYS;
agx_pack_rasterizer_face(&so->front,
z_func, !state->depth_writemask);
state->stencil[0], z_func, !state->depth_writemask);
if (state->stencil[1].enabled) {
agx_pack_rasterizer_face(&so->back,
z_func, !state->depth_writemask);
state->stencil[1], z_func, !state->depth_writemask);
} else {
/* One sided stencil */
so->back = so->front;
@@ -1295,6 +1327,11 @@ demo_rasterizer(struct agx_context *ctx, struct agx_pool *pool)
struct agx_rasterizer_packed out;
agx_pack(&out, RASTERIZER, cfg) {
bool back_stencil = ctx->zs.base.stencil[1].enabled;
cfg.front.stencil_reference = ctx->stencil_ref.ref_value[0];
cfg.back.stencil_reference = back_stencil ?
ctx->stencil_ref.ref_value[1] :
cfg.front.stencil_reference;
cfg.front.line_width = cfg.back.line_width = rast->line_width;
cfg.front.polygon_mode = cfg.back.polygon_mode = AGX_POLYGON_MODE_FILL;