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i965: Attempt to un-muddle Gen6 data port message target defines.

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These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public
Sandybridge documentation/SEND instruction description).

Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE
which just happened to be the same values as Render Cache/Sampler Cache.
It turns out that this field has nothing to do with READ/WRITE on
Sandybridge, but rather represents which data port to direct it to.

This was especially confusing in brw_set_dp_read_message, which
used "BRW_MESSAGE_TARGET_DATAPORT_WRITE."  In a read function.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
2011-05-13 07:49:27 -07:00
parent 5f5d486717
commit 17eaff77b0
2 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_defines.h
+6 -3
View File
@@ -663,11 +663,14 @@
#define BRW_MESSAGE_TARGET_MATH 1 /* reserved on GEN6 */
#define BRW_MESSAGE_TARGET_SAMPLER 2
#define BRW_MESSAGE_TARGET_GATEWAY 3
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 /* sampler cache on GEN6 */
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 /* render cache on Gen6 */
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5
#define BRW_MESSAGE_TARGET_URB 6
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7
#define BRW_MESSAGE_TARGET_CONST_CACHE 9 /* GEN6 */
#define GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE 4
#define GEN6_MESSAGE_TARGET_DP_RENDER_CACHE 5
#define GEN6_MESSAGE_TARGET_DP_CONST_CACHE 9
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
src/mesa/drivers/dri/i965/brw_eu_emit.c
+3 -3
View File
@@ -498,7 +498,7 @@ static void brw_set_dp_write_message( struct brw_context *brw,
insn->bits3.dp_render_cache.end_of_thread = end_of_thread;
/* We always use the render cache for write messages */
insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
} else if (intel->gen == 5) {
insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_write_gen5.msg_control = msg_control;
@@ -541,9 +541,9 @@ brw_set_dp_read_message(struct brw_context *brw,
uint32_t target_function;
if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE)
target_function = BRW_MESSAGE_TARGET_DATAPORT_READ; /* data cache */
target_function = GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE;
else
target_function = BRW_MESSAGE_TARGET_DATAPORT_WRITE; /* render cache */
target_function = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
insn->bits3.dp_render_cache.binding_table_index = binding_table_index;
insn->bits3.dp_render_cache.msg_control = msg_control;