intel: Try forcing flushes
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@@ -68,6 +68,8 @@ intel_be_offset_relocation(struct intel_be_batchbuffer *batch,
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offset = (unsigned)(batch->base.ptr - batch->base.map);
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debug_printf(" - offset: %p\n", offset);
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ret = drm_intel_bo_emit_reloc(batch->bo, offset,
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bo, pre_add,
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read_domains,
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@@ -96,14 +98,12 @@ intel_be_batchbuffer_flush(struct intel_be_batchbuffer *batch,
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assert((used & 3) == 0);
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if (used & 4) {
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((uint32_t *) batch->base.ptr)[0] = ((0<<29)|(4<<23)); // MI_FLUSH;
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((uint32_t *) batch->base.ptr)[1] = 0;
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((uint32_t *) batch->base.ptr)[2] = (0xA<<23); // MI_BATCH_BUFFER_END;
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batch->base.ptr += 12;
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i915_batchbuffer_dword(i915, (0x0<<29)|(0x4<<23)|(1<<0)); // MI_FLUSH | FLUSH_MAP_CACHE;
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i915_batchbuffer_dword(i915, (0x0<<29)|(0x0<<23)); // MI_NOOP
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i915_batchbuffer_dword(i915, (0x0<<29)|(0xA<<23)); // MI_BATCH_BUFFER_END;
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} else {
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((uint32_t *) batch->base.ptr)[0] = ((0<<29)|(4<<23)); // MI_FLUSH;
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((uint32_t *) batch->base.ptr)[1] = (0xA<<23); // MI_BATCH_BUFFER_END;
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batch->base.ptr += 8;
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i915_batchbuffer_dword(i915, (0x0<<29)|(0x4<<23)|(1<<0)); //MI_FLUSH | FLUSH_MAP_CACHE;
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i915_batchbuffer_dword(i915, (0x0<<29)|(0xA<<23)); // MI_BATCH_BUFFER_END;
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}
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i915_dump_batchbuffer(i915);
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