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radv: copy ia_multi_vgt_param to the cmdbuf state

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22194>
This commit is contained in:
Samuel Pitoiset
2023-03-29 18:50:27 +02:00
committed by Marge Bot
parent 0daffade14
commit 15f1d5cc8f
3 changed files with 15 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+2
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@@ -6584,6 +6584,8 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
cmd_buffer->state.custom_blend_mode = graphics_pipeline->custom_blend_mode;
cmd_buffer->state.rast_prim = graphics_pipeline->rast_prim;
cmd_buffer->state.ia_multi_vgt_param = graphics_pipeline->ia_multi_vgt_param;
break;
}
default:
src/amd/vulkan/radv_private.h
+9 -7
View File
@@ -1577,6 +1577,13 @@ struct radv_multisample_state {
float min_sample_shading;
};
struct radv_ia_multi_vgt_param_helpers {
uint32_t base;
bool partial_es_wave;
bool ia_switch_on_eoi;
bool partial_vs_wave;
};
struct radv_cmd_state {
/* Vertex descriptors */
uint64_t vb_va;
@@ -1687,6 +1694,8 @@ struct radv_cmd_state {
/* Whether this commandbuffer uses performance counters. */
bool uses_perf_counters;
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
/* Tessellation info when patch control points is dynamic. */
unsigned tess_num_patches;
unsigned tess_lds_size;
@@ -2133,13 +2142,6 @@ struct radv_prim_vertex_count {
uint8_t incr;
};
struct radv_ia_multi_vgt_param_helpers {
uint32_t base;
bool partial_es_wave;
bool ia_switch_on_eoi;
bool partial_vs_wave;
};
#define SI_GS_PER_ES 128
enum radv_pipeline_type {
src/amd/vulkan/si_cmd_buffer.c
+4 -5
View File
@@ -837,14 +837,13 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra
unsigned patch_control_points, unsigned num_tess_patches)
{
const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const unsigned max_primgroup_in_wave = 2;
/* SWITCH_ON_EOP(0) is always preferable. */
bool wd_switch_on_eop = false;
bool ia_switch_on_eop = false;
bool ia_switch_on_eoi = false;
bool partial_vs_wave = false;
bool partial_es_wave = pipeline->ia_multi_vgt_param.partial_es_wave;
bool partial_es_wave = cmd_buffer->state.ia_multi_vgt_param.partial_es_wave;
bool multi_instances_smaller_than_primgroup;
struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
unsigned primgroup_size;
@@ -878,8 +877,8 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra
multi_instances_smaller_than_primgroup = true;
}
ia_switch_on_eoi = pipeline->ia_multi_vgt_param.ia_switch_on_eoi;
partial_vs_wave = pipeline->ia_multi_vgt_param.partial_vs_wave;
ia_switch_on_eoi = cmd_buffer->state.ia_multi_vgt_param.ia_switch_on_eoi;
partial_vs_wave = cmd_buffer->state.ia_multi_vgt_param.partial_vs_wave;
if (info->gfx_level >= GFX7) {
/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
@@ -963,7 +962,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_dra
partial_vs_wave = true;
}
return pipeline->ia_multi_vgt_param.base | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
return cmd_buffer->state.ia_multi_vgt_param.base | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |