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ir3: Add ir3_collect() for fixed-size collects

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This avoids having the specify the size, and fixes weird formatting with
clang-format.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11801>
This commit is contained in:
Connor Abbott
2021-07-12 18:11:21 +02:00
committed by Marge Bot
parent 49a39fbf0c
commit 1514744a16
4 changed files with 30 additions and 72 deletions
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src/freedreno/ir3/ir3_a4xx.c
+6 -24
View File
@@ -48,10 +48,7 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
offset = ir3_get_src(ctx, &intr->src[2])[0];
/* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
byte_offset,
create_immed(b, 0),
}, 2);
src0 = ir3_collect(ctx, byte_offset, create_immed(b, 0));
src1 = offset;
ldgb = ir3_LDGB(b, ssbo, 0,
@@ -87,10 +84,7 @@ emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
*/
src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
src1 = offset;
src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
byte_offset,
create_immed(b, 0),
}, 2);
src2 = ir3_collect(ctx, byte_offset, create_immed(b, 0));
stgb = ir3_STGB(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
stgb->cat6.iim_val = ncomp;
@@ -140,10 +134,7 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
*/
src0 = ir3_get_src(ctx, &intr->src[2])[0];
src1 = offset;
src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
byte_offset,
create_immed(b, 0),
}, 2);
src2 = ir3_collect(ctx, byte_offset, create_immed(b, 0));
switch (intr->intrinsic) {
case nir_intrinsic_ssbo_atomic_add_ir3:
@@ -177,10 +168,7 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
/* for cmpxchg, src0 is [ui]vec2(data, compare): */
src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
ir3_get_src(ctx, &intr->src[3])[0],
src0,
}, 2);
src0 = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[3])[0], src0);
src1 = ir3_get_src(ctx, &intr->src[4])[0];
atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
break;
@@ -239,10 +227,7 @@ get_image_offset(struct ir3_context *ctx, const nir_intrinsic_instr *instr,
offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
}
return ir3_create_collect(ctx, (struct ir3_instruction*[]){
offset,
create_immed(b, 0),
}, 2);
return ir3_collect(ctx, offset, create_immed(b, 0));
}
/* src[] = { index, coord, sample_index, value }. const_index[] = {} */
@@ -327,10 +312,7 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_image_atomic_comp_swap:
/* for cmpxchg, src0 is [ui]vec2(data, compare): */
src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
ir3_get_src(ctx, &intr->src[4])[0],
src0,
}, 2);
src0 = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[4])[0], src0);
atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
break;
default:
src/freedreno/ir3/ir3_a6xx.c
+8 -18
View File
@@ -136,14 +136,10 @@ emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap_ir3) {
src0 = ir3_get_src(ctx, &intr->src[4])[0];
struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0];
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
dummy, compare, data
}, 3);
src1 = ir3_collect(ctx, dummy, compare, data);
} else {
src0 = ir3_get_src(ctx, &intr->src[3])[0];
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
dummy, data
}, 2);
src1 = ir3_collect(ctx, dummy, data);
}
switch (intr->intrinsic) {
@@ -284,13 +280,9 @@ emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
if (intr->intrinsic == nir_intrinsic_image_atomic_comp_swap ||
intr->intrinsic == nir_intrinsic_bindless_image_atomic_comp_swap) {
struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
dummy, compare, value
}, 3);
src1 = ir3_collect(ctx, dummy, compare, value);
} else {
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
dummy, value
}, 2);
src1 = ir3_collect(ctx, dummy, value);
}
switch (intr->intrinsic) {
@@ -379,10 +371,9 @@ emit_intrinsic_load_global_ir3(struct ir3_context *ctx, nir_intrinsic_instr *int
unsigned dest_components = nir_intrinsic_dest_components(intr);
struct ir3_instruction *addr, *offset;
addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
addr = ir3_collect(ctx,
ir3_get_src(ctx, &intr->src[0])[0],
ir3_get_src(ctx, &intr->src[0])[1]
}, 2);
ir3_get_src(ctx, &intr->src[0])[1]);
offset = ir3_get_src(ctx, &intr->src[1])[0];
@@ -407,10 +398,9 @@ emit_intrinsic_store_global_ir3(struct ir3_context *ctx, nir_intrinsic_instr *in
struct ir3_instruction *value, *addr, *offset;
unsigned ncomp = nir_intrinsic_src_components(intr, 0);
addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
addr = ir3_collect(ctx,
ir3_get_src(ctx, &intr->src[1])[0],
ir3_get_src(ctx, &intr->src[1])[1]
}, 2);
ir3_get_src(ctx, &intr->src[1])[1]);
offset = ir3_get_src(ctx, &intr->src[2])[0];
src/freedreno/ir3/ir3_compiler_nir.c
+11 -30
View File
@@ -838,7 +838,7 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
carry->cat2.condition = IR3_COND_LT;
base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
addr = ir3_collect(ctx, addr, base_hi);
}
for (int i = 0; i < intr->num_components; i++) {
@@ -1058,10 +1058,7 @@ emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_shared_atomic_comp_swap:
/* for cmpxchg, src1 is [ui]vec2(data, compare): */
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
ir3_get_src(ctx, &intr->src[2])[0],
src1,
}, 2);
src1 = ir3_collect(ctx, ir3_get_src(ctx, &intr->src[2])[0], src1);
atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
break;
default:
@@ -1185,10 +1182,7 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
texture = ir3_get_src(ctx, &intr->src[0])[0];
sampler = create_immed(b, 0);
info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
texture,
sampler,
}, 2);
info.samp_tex = ir3_collect(ctx, texture, sampler);
}
} else {
info.flags |= IR3_INSTR_S2EN;
@@ -1199,10 +1193,7 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
sampler,
texture,
}, 2);
info.samp_tex = ir3_collect(ctx, sampler, texture);
}
return info;
@@ -2346,10 +2337,7 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
} else {
sampler = create_immed(b, 0);
}
info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
texture,
sampler,
}, 2);
info.samp_tex = ir3_collect(ctx, texture, sampler);
}
} else {
info.flags |= IR3_INSTR_S2EN;
@@ -2377,10 +2365,7 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
info.samp_idx = tex->texture_index;
}
info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
sampler,
texture,
}, 2);
info.samp_tex = ir3_collect(ctx, sampler, texture);
}
return info;
@@ -2621,10 +2606,9 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
ctx->so->fb_read = true;
info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
info.samp_tex = ir3_collect(ctx,
create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
}, 2);
create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16));
info.flags = IR3_INSTR_S2EN;
ctx->so->num_samp++;
@@ -3960,8 +3944,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
unsigned n = so->outputs_count++;
so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
struct ir3_instruction *out =
ir3_create_collect(ctx, &ctx->primitive_id, 1);
struct ir3_instruction *out = ir3_collect(ctx, ctx->primitive_id);
outputs[outputs_count] = out;
outidxs[outputs_count] = n;
regids[outputs_count] = regid(0, 1);
@@ -3971,8 +3954,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
if (ctx->gs_header) {
unsigned n = so->outputs_count++;
so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
struct ir3_instruction *out =
ir3_create_collect(ctx, &ctx->gs_header, 1);
struct ir3_instruction *out = ir3_collect(ctx, ctx->gs_header);
outputs[outputs_count] = out;
outidxs[outputs_count] = n;
regids[outputs_count] = regid(0, 0);
@@ -3982,8 +3964,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
if (ctx->tcs_header) {
unsigned n = so->outputs_count++;
so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
struct ir3_instruction *out =
ir3_create_collect(ctx, &ctx->tcs_header, 1);
struct ir3_instruction *out = ir3_collect(ctx, ctx->tcs_header);
outputs[outputs_count] = out;
outidxs[outputs_count] = n;
regids[outputs_count] = regid(0, 0);
src/freedreno/ir3/ir3_context.h
+5
View File
@@ -197,6 +197,11 @@ void ir3_handle_nonuniform(struct ir3_instruction *instr, nir_intrinsic_instr *i
void emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
struct ir3_instruction **dst);
#define ir3_collect(ctx, ...) ({ \
struct ir3_instruction *__arr[] = { __VA_ARGS__ }; \
ir3_create_collect(ctx, __arr, ARRAY_SIZE(__arr)); \
})
NORETURN void ir3_context_error(struct ir3_context *ctx, const char *format, ...);
#define compile_assert(ctx, cond) do { \