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radv: re-format using clang-format

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No manual changes here, this is simply running
$ ninja -C build/ clang-format

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37226>
This commit is contained in:
Christian Gmeiner
2025-09-08 13:10:16 +02:00
committed by Marge Bot
parent dcfa4fafca
commit 1492de1bc3
11 changed files with 60 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/bvh/encode.h
+2 -1
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@@ -135,7 +135,8 @@ bit_writer_finish(inout bit_writer writer)
writer.total_count = 0;
}
#define RADV_GFX12_UPDATABLE_PRIMITIVE_NODE_INDICES_OFFSET (align(RADV_GFX12_PRIMITIVE_NODE_HEADER_SIZE, 32) / 8 + 9 * 4)
#define RADV_GFX12_UPDATABLE_PRIMITIVE_NODE_INDICES_OFFSET \
(align(RADV_GFX12_PRIMITIVE_NODE_HEADER_SIZE, 32) / 8 + 9 * 4)
void
radv_encode_triangle_gfx12(VOID_REF dst, vk_ir_triangle_node src)
src/amd/vulkan/nir/radv_meta_nir.c
+7 -9
View File
@@ -507,8 +507,8 @@ radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d)
nir_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range = 16);
nir_def *img_coord = nir_iadd(&b, global_id, offset);
nir_def *outval = nir_txf(&b, nir_trim_vector(&b, img_coord, 2 + is_3d),
.texture_deref = nir_build_deref_var(&b, input_img));
nir_def *outval =
nir_txf(&b, nir_trim_vector(&b, img_coord, 2 + is_3d), .texture_deref = nir_build_deref_var(&b, input_img));
nir_def *pos_x = nir_channel(&b, global_id, 0);
nir_def *pos_y = nir_channel(&b, global_id, 1);
@@ -649,7 +649,8 @@ radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bo
nir_def *tex_vals[8];
if (is_multisampled) {
for (uint32_t i = 0; i < samples; i++) {
tex_vals[i] = nir_txf_ms(&b, nir_trim_vector(&b, src_coord, 2), nir_imm_int(&b, i), .texture_deref = input_img_deref);
tex_vals[i] =
nir_txf_ms(&b, nir_trim_vector(&b, src_coord, 2), nir_imm_int(&b, i), .texture_deref = input_img_deref);
}
} else {
tex_vals[0] = nir_txf(&b, nir_trim_vector(&b, src_coord, 2 + src_3d), .texture_deref = input_img_deref);
@@ -1179,10 +1180,8 @@ radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int sampl
nir_def *dst_coord = nir_vec4(&b, nir_channel(&b, src_coord, 0), nir_channel(&b, src_coord, 1), nir_undef(&b, 1, 32),
nir_undef(&b, 1, 32));
nir_def *frag_mask =
nir_build_tex(&b, nir_texop_fragment_mask_fetch_amd,
.coord = src_coord,
.texture_deref = nir_build_deref_var(&b, input_img));
nir_def *frag_mask = nir_build_tex(&b, nir_texop_fragment_mask_fetch_amd, .coord = src_coord,
.texture_deref = nir_build_deref_var(&b, input_img));
/* Get the maximum sample used in this fragment. */
nir_def *max_sample_index = nir_imm_int(&b, 0);
@@ -1198,8 +1197,7 @@ radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int sampl
nir_loop *loop = nir_push_loop(&b);
{
nir_def *sample_id = nir_load_var(&b, counter);
nir_def *outval = nir_build_tex(&b, nir_texop_fragment_fetch_amd,
.coord = src_coord, .ms_index = sample_id,
nir_def *outval = nir_build_tex(&b, nir_texop_fragment_fetch_amd, .coord = src_coord, .ms_index = sample_id,
.texture_deref = nir_build_deref_var(&b, input_img));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->def, dst_coord, sample_id, outval,
src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c
+3 -4
View File
@@ -325,10 +325,9 @@ lower_load_vs_input(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs
* Typed loads can cause GPU hangs when used with improper alignment.
*/
if (can_use_untyped_load(f, bit_size)) {
loads[num_loads++] = nir_load_buffer_amd(b, channels, bit_size, descriptor, zero, zero, index,
.base = const_off, .memory_modes = nir_var_shader_in,
.align_mul = align_mul, .align_offset = align_offset,
.access = ACCESS_CAN_REORDER | ACCESS_CAN_SPECULATE);
loads[num_loads++] = nir_load_buffer_amd(
b, channels, bit_size, descriptor, zero, zero, index, .base = const_off, .memory_modes = nir_var_shader_in,
.align_mul = align_mul, .align_offset = align_offset, .access = ACCESS_CAN_REORDER | ACCESS_CAN_SPECULATE);
} else {
loads[num_loads++] = nir_load_typed_buffer_amd(
b, channels, bit_size, descriptor, zero, zero, index, .base = const_off, .format = fetch_format,
src/amd/vulkan/nir/radv_nir_rt_common.c
+9 -8
View File
@@ -289,12 +289,12 @@ intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, nir_d
*
* Any set of two triangles with two shared vertices that were specified in the same
* winding order in each triangle have a shared edge defined by those vertices.
*
*
* This means we can decide which triangle should intersect by comparing the shared edge
* to two arbitrary directions because the shared edges are antiparallel. The triangle
* vertices are transformed so the ray direction is (0 0 1). Therefore it makes sense to
* choose (1 0 0) and (0 1 0) as reference directions.
*
*
* Hitting edges is extremely rare so an if should be worth.
*/
nir_def *is_edge_a = nir_feq_imm(b, u, 0.0f);
@@ -307,25 +307,26 @@ intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, nir_d
nir_def *intersect_edge_a = nir_iand(b, is_edge_a, radv_build_intersect_edge(b, bx, by, cx, cy));
nir_def *intersect_edge_b = nir_iand(b, is_edge_b, radv_build_intersect_edge(b, cx, cy, ax, ay));
nir_def *intersect_edge_c = nir_iand(b, is_edge_c, radv_build_intersect_edge(b, ax, ay, bx, by));
intersect_edge = nir_iand(b, intersect_edge, nir_ior(b, nir_ior(b, intersect_edge_a, intersect_edge_b), intersect_edge_c));
intersect_edge =
nir_iand(b, intersect_edge, nir_ior(b, nir_ior(b, intersect_edge_a, intersect_edge_b), intersect_edge_c));
/* For vertices, special handling is needed to avoid double hits. The spec defines
* shared vertices as follows (Vulkan 1.4.322, Section 40.1.1 Watertightness):
*
* Any set of two or more triangles where all triangles have one vertex with an
* identical position value, that vertex is a shared vertex.
*
*
* Since the no double hit/miss requirement of a shared vertex is only formulated for
* closed fans
*
*
* Implementations should not double-hit or miss when a ray intersects a shared edge,
* or a shared vertex of a closed fan.
*
*
* it is possible to choose an arbitrary direction n that defines which triangle in the
* closed fan should intersect the shared vertex with the ray.
*
*
* All edges that include the above vertex are shared edges.
*
*
* Implies that all triangles have the same winding order. It is therefore sufficiant
* to choose the triangle where the other vertices are on both sides of a plane
* perpendicular to n (relying on winding order to get one instead of two triangles
src/amd/vulkan/radv_constants.h
+4 -4
View File
@@ -142,9 +142,9 @@
#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
/* Descriptor sizes */
#define RADV_SAMPLER_DESC_SIZE 16
#define RADV_STORAGE_IMAGE_DESC_SIZE 32
#define RADV_BUFFER_DESC_SIZE 16
#define RADV_ACCEL_STRUCT_DESC_SIZE 16
#define RADV_SAMPLER_DESC_SIZE 16
#define RADV_STORAGE_IMAGE_DESC_SIZE 32
#define RADV_BUFFER_DESC_SIZE 16
#define RADV_ACCEL_STRUCT_DESC_SIZE 16
#endif /* RADV_CONSTANTS_H */
src/amd/vulkan/radv_dgc.c
+1 -1
View File
@@ -25,7 +25,7 @@
/* Arbitrary limit of the maximum number of sequences per IB to simplify the DGC IB chaining
* implementation which is already quite complicated.
*/
#define MAX_SEQUENCES_PER_IB 65536
#define MAX_SEQUENCES_PER_IB 65536
/* The DGC command buffer layout is quite complex, here's some explanations:
*
src/amd/vulkan/radv_physical_device.c
+20 -20
View File
@@ -3032,29 +3032,28 @@ struct matrix_prop {
bool saturate;
};
static void fill_matrix_prop_khr(struct __vk_outarray *base,
struct matrix_prop *prop)
static void
fill_matrix_prop_khr(struct __vk_outarray *base, struct matrix_prop *prop)
{
vk_outarray(VkCooperativeMatrixPropertiesKHR) *out = (void *)base;
vk_outarray_append_typed(VkCooperativeMatrixPropertiesKHR, out, p)
{
*p = (struct VkCooperativeMatrixPropertiesKHR){
.sType = VK_STRUCTURE_TYPE_COOPERATIVE_MATRIX_PROPERTIES_KHR,
.MSize = 16,
.NSize = 16,
.KSize = 16,
.AType = prop->a_type,
.BType = prop->b_type,
.CType = prop->c_type,
.ResultType = prop->r_type,
.saturatingAccumulation = prop->saturate,
.scope = VK_SCOPE_SUBGROUP_KHR};
*p = (struct VkCooperativeMatrixPropertiesKHR){.sType = VK_STRUCTURE_TYPE_COOPERATIVE_MATRIX_PROPERTIES_KHR,
.MSize = 16,
.NSize = 16,
.KSize = 16,
.AType = prop->a_type,
.BType = prop->b_type,
.CType = prop->c_type,
.ResultType = prop->r_type,
.saturatingAccumulation = prop->saturate,
.scope = VK_SCOPE_SUBGROUP_KHR};
}
}
static void fill_flexible_matrix_prop_nv(struct __vk_outarray *base,
struct matrix_prop *prop)
static void
fill_flexible_matrix_prop_nv(struct __vk_outarray *base, struct matrix_prop *prop)
{
vk_outarray(VkCooperativeMatrixFlexibleDimensionsPropertiesNV) *out = (void *)base;
@@ -3074,9 +3073,9 @@ static void fill_flexible_matrix_prop_nv(struct __vk_outarray *base,
}
}
static void fill_array_sizes_structs(const struct radv_physical_device *pdev,
struct __vk_outarray *base,
void (*array_size_cb)(struct __vk_outarray *base, struct matrix_prop *prop))
static void
fill_array_sizes_structs(const struct radv_physical_device *pdev, struct __vk_outarray *base,
void (*array_size_cb)(struct __vk_outarray *base, struct matrix_prop *prop))
{
/* The Vulkan spec says:
* If some types are preferred over other types (e.g. for performance),
@@ -3140,8 +3139,9 @@ radv_GetPhysicalDeviceCooperativeMatrixPropertiesKHR(VkPhysicalDevice physicalDe
}
VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPhysicalDeviceCooperativeMatrixFlexibleDimensionsPropertiesNV(VkPhysicalDevice physicalDevice, uint32_t *pPropertyCount,
VkCooperativeMatrixFlexibleDimensionsPropertiesNV *pProperties)
radv_GetPhysicalDeviceCooperativeMatrixFlexibleDimensionsPropertiesNV(
VkPhysicalDevice physicalDevice, uint32_t *pPropertyCount,
VkCooperativeMatrixFlexibleDimensionsPropertiesNV *pProperties)
{
VK_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
VK_OUTARRAY_MAKE_TYPED(VkCooperativeMatrixFlexibleDimensionsPropertiesNV, out, pProperties, pPropertyCount);
src/amd/vulkan/radv_shader.h
+6 -4
View File
@@ -34,14 +34,16 @@ struct radv_shader_args;
struct radv_serialized_shader_arena_block;
struct vk_pipeline_robustness_state;
#define RADV_GRAPHICS_STAGE_BITS (VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_TASK_BIT_EXT)
#define RADV_RT_STAGE_BITS (VK_SHADER_STAGE_RAYGEN_BIT_KHR | VK_SHADER_STAGE_ANY_HIT_BIT_KHR | VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR | \
VK_SHADER_STAGE_MISS_BIT_KHR | VK_SHADER_STAGE_INTERSECTION_BIT_KHR | VK_SHADER_STAGE_CALLABLE_BIT_KHR)
#define RADV_GRAPHICS_STAGE_BITS \
(VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_TASK_BIT_EXT)
#define RADV_RT_STAGE_BITS \
(VK_SHADER_STAGE_RAYGEN_BIT_KHR | VK_SHADER_STAGE_ANY_HIT_BIT_KHR | VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR | \
VK_SHADER_STAGE_MISS_BIT_KHR | VK_SHADER_STAGE_INTERSECTION_BIT_KHR | VK_SHADER_STAGE_CALLABLE_BIT_KHR)
#define RADV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1)
#define radv_foreach_stage(stage, stage_bits) \
for (mesa_shader_stage stage, __tmp = (mesa_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
for (mesa_shader_stage stage, __tmp = (mesa_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
stage = ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
enum radv_nggc_settings {
src/amd/vulkan/radv_video.c
+2 -2
View File
@@ -2477,8 +2477,8 @@ fill_ref_buffer(rvcn_dec_ref_buffer_t *ref, struct radv_image *img, uint32_t sli
static bool
rvcn_dec_message_decode(struct radv_cmd_buffer *cmd_buffer, struct radv_video_session *vid,
struct vk_video_session_parameters *params, void *ptr, void *it_probs_ptr, uint32_t *slice_offset,
const struct VkVideoDecodeInfoKHR *frame_info)
struct vk_video_session_parameters *params, void *ptr, void *it_probs_ptr,
uint32_t *slice_offset, const struct VkVideoDecodeInfoKHR *frame_info)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
src/amd/vulkan/radv_video_enc.c
+4 -8
View File
@@ -3253,14 +3253,12 @@ radv_GetEncodedVideoSessionParametersKHR(VkDevice device,
vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_GET_INFO_KHR);
size_t sps_size = 0, pps_size = 0;
if (h264_get_info->writeStdSPS) {
const StdVideoH264SequenceParameterSet *sps =
vk_video_find_h264_enc_std_sps(templ, h264_get_info->stdSPSId);
const StdVideoH264SequenceParameterSet *sps = vk_video_find_h264_enc_std_sps(templ, h264_get_info->stdSPSId);
assert(sps);
vk_video_encode_h264_sps(sps, size_limit, &sps_size, pData);
}
if (h264_get_info->writeStdPPS) {
const StdVideoH264PictureParameterSet *pps =
vk_video_find_h264_enc_std_pps(templ, h264_get_info->stdPPSId);
const StdVideoH264PictureParameterSet *pps = vk_video_find_h264_enc_std_pps(templ, h264_get_info->stdPPSId);
assert(pps);
char *data_ptr = pData ? (char *)pData + sps_size : NULL;
vk_video_encode_h264_pps(pps, templ->h264_enc.profile_idc == STD_VIDEO_H264_PROFILE_IDC_HIGH, size_limit,
@@ -3286,15 +3284,13 @@ radv_GetEncodedVideoSessionParametersKHR(VkDevice device,
vk_video_encode_h265_vps(vps, size_limit, &vps_size, pData);
}
if (h265_get_info->writeStdSPS) {
const StdVideoH265SequenceParameterSet *sps =
vk_video_find_h265_enc_std_sps(templ, h265_get_info->stdSPSId);
const StdVideoH265SequenceParameterSet *sps = vk_video_find_h265_enc_std_sps(templ, h265_get_info->stdSPSId);
assert(sps);
char *data_ptr = pData ? (char *)pData + vps_size : NULL;
vk_video_encode_h265_sps(sps, size_limit, &sps_size, data_ptr);
}
if (h265_get_info->writeStdPPS) {
const StdVideoH265PictureParameterSet *pps =
vk_video_find_h265_enc_std_pps(templ, h265_get_info->stdPPSId);
const StdVideoH265PictureParameterSet *pps = vk_video_find_h265_enc_std_pps(templ, h265_get_info->stdPPSId);
assert(pps);
char *data_ptr = pData ? (char *)pData + vps_size + sps_size : NULL;
vk_video_encode_h265_pps(pps, size_limit, &pps_size, data_ptr);
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+2 -2
View File
@@ -735,8 +735,8 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
struct radv_amdgpu_winsys *ws = parent->ws;
const bool use_ib2 = parent->use_ib && !parent->is_secondary && allow_ib2 && parent->hw_ip == AMD_IP_GFX &&
ws->info.gfx_level >= GFX7;
const bool use_ib2 =
parent->use_ib && !parent->is_secondary && allow_ib2 && parent->hw_ip == AMD_IP_GFX && ws->info.gfx_level >= GFX7;
if (parent->status != VK_SUCCESS || child->status != VK_SUCCESS)
return;