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radv, aco: Packed iadd_sat/uadd_sat.

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Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15421>
This commit is contained in:
Georg Lehmann
2022-01-20 20:50:15 +01:00
committed by Marge Bot
parent 6b662a4f0c
commit 141ca78634
3 changed files with 16 additions and 0 deletions
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12
src/amd/compiler/aco_instruction_selection.cpp
View File

@@ -1823,6 +1823,12 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
break;
}
case nir_op_uadd_sat: {
if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
Instruction* add_instr =
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_u16, dst);
add_instr->vop3p().clamp = 1;
break;
}
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src1 = get_alu_src(ctx, instr->src[1]);
if (dst.regClass() == s1) {
@@ -1901,6 +1907,12 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
break;
}
case nir_op_iadd_sat: {
if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
Instruction* add_instr =
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_i16, dst);
add_instr->vop3p().clamp = 1;
break;
}
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src1 = get_alu_src(ctx, instr->src[1]);
if (dst.regClass() == s1) {

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@@ -557,6 +557,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_b2f32:
case nir_op_mov: break;
case nir_op_iadd:
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_imul:
case nir_op_imin:

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -3667,6 +3667,8 @@ opt_vectorize_callback(const nir_instr *instr, void *_)
case nir_op_fmin:
case nir_op_fmax:
case nir_op_iadd:
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_imul:
case nir_op_imin: