radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)

2012-05-23 14:48:36 -04:00
parent 3059c075a7
commit 1404e6b9fc
8 changed files with 8 additions and 422 deletions
@@ -36,7 +36,6 @@ my @F32_MULTICLASSES = qw {
 };

 my @I32_MULTICLASSES = qw {
-  BinaryOpMCInt
  BinaryOpMCi32
  BinaryOpMCi32Const
 };
@@ -54,7 +53,7 @@ my $FILE_TYPE = $ARGV[0];

 open AMDIL, '<', 'AMDILInstructions.td';

-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ');

 while (<AMDIL>) {
  if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
@@ -210,22 +210,6 @@ def uctof_f32:Pat < (f32 (uint_to_fp GPRI8:$src)),
   (LOADCONST_i32 24)))) >;


-def ftosc_i8:Pat < (i8 (fp_to_sint GPRF32:$src)),
-(i8
- (IL_ASCHAR_i32
-  (BINARY_AND_i32
-(FTOI GPRF32:$src),
-   (LOADCONST_i32 0x000000FF)))) >;
-
-
-def ftouc_i8:Pat < (i8 (fp_to_uint GPRF32:$src)),
-(i8
- (IL_ASCHAR_i32
-  (BINARY_AND_i32
-(FTOU GPRF32:$src),
-   (LOADCONST_i32 0x000000FF)))) >;
-
-
 def sctod_f64:Pat < (f64 (sint_to_fp GPRI8:$src)),
 (f64 (FTOD
      (ITOF
@@ -245,23 +229,6 @@ def uctod_f64:Pat < (f64 (uint_to_fp GPRI8:$src)),
   (LOADCONST_i32 24)),
  (LOADCONST_i32 24))))) >;

-
-def dtosc_i8:Pat < (i8 (fp_to_sint GPRF64:$src)),
-(i8
- (IL_ASCHAR_i32
-  (BINARY_AND_i32
-(FTOI (DTOF GPRF64:$src)),
-   (LOADCONST_i32 0x000000FF)))) >;
-
-
-def dtouc_i8:Pat < (i8 (fp_to_uint GPRF64:$src)),
-(i8
- (IL_ASCHAR_i32
-  (BINARY_AND_i32
-(FTOU (DTOF GPRF64:$src)),
-   (LOADCONST_i32 0x000000FF)))) >;
-
-
 def sstof_f32:Pat < (f32 (sint_to_fp GPRI16:$src)),
 (f32
 (ITOF
@@ -281,23 +248,6 @@ def ustof_f32:Pat < (f32 (uint_to_fp GPRI16:$src)),
    (LOADCONST_i32 16)),
   (LOADCONST_i32 16)))) >;

-
-def ftoss_i16:Pat < (i16 (fp_to_sint GPRF32:$src)),
-(i16
- (IL_ASSHORT_i32
-  (BINARY_AND_i32
-(FTOI GPRF32:$src),
-   (LOADCONST_i32 0x0000FFFF)))) >;
-
-
-def ftous_i16:Pat < (i16 (fp_to_uint GPRF32:$src)),
-(i16
- (IL_ASSHORT_i32
-  (BINARY_AND_i32
-(FTOU GPRF32:$src),
-   (LOADCONST_i32 0x0000FFFF)))) >;
-
-
 def sstod_f64:Pat < (f64 (sint_to_fp GPRI16:$src)),
 (f64 (FTOD
      (ITOF
@@ -318,73 +268,6 @@ def ustod_f64:Pat < (f64 (uint_to_fp GPRI16:$src)),
  (LOADCONST_i32 16))))) >;


-def dtoss_i16:Pat < (i16 (fp_to_sint GPRF64:$src)),
-(i16
- (IL_ASSHORT_i32
-  (BINARY_AND_i32
-(FTOI (DTOF GPRF64:$src)),
-   (LOADCONST_i32 0x0000FFFF)))) >;
-
-
-def dtous_i16:Pat < (i16 (fp_to_uint GPRF64:$src)),
-(i16
- (IL_ASSHORT_i32
-  (BINARY_AND_i32
-(FTOU (DTOF GPRF64:$src)),
-   (LOADCONST_i32 0x0000FFFF)))) >;
-
-
-
-
-
-def stoc_i8:Pat < (i8 (trunc GPRI16:$src)),
-(IL_ASCHAR_i32
-   (IL_ASINT_i16
-(BINARY_AND_i16 GPRI16:$src,
-     (LOADCONST_i16 0x000000FF)))
-  ) >;
-
-
-def itoc_i8:Pat < (i8 (trunc GPRI32:$src)),
-(IL_ASCHAR_i32
-   (IL_ASINT_i32
-(BINARY_AND_i32 GPRI32:$src,
-     (LOADCONST_i32 0x000000FF)))
-  ) >;
-
-
-def itos_i16:Pat < (i16 (trunc GPRI32:$src)),
-(IL_ASSHORT_i32
-   (IL_ASINT_i32
-(BINARY_AND_i32 GPRI32:$src,
-     (LOADCONST_i32 0x0000FFFF)))
-  ) >;
-
-
-def ltoc_i8:Pat < (i8 (trunc GPRI64:$src)),
-(IL_ASCHAR_i32
-   (BINARY_AND_i32
-(LLO GPRI64:$src),
-    (LOADCONST_i32 0x000000FF))
-  ) >;
-
-
-def ltos_i16:Pat < (i16 (trunc GPRI64:$src)),
-(IL_ASSHORT_i32
-   (BINARY_AND_i32
-(LLO GPRI64:$src),
-    (LOADCONST_i32 0x0000FFFF))
-  ) >;
-
-
-def ltoi_i32:Pat < (i32 (trunc GPRI64:$src)),
-(IL_ASINT_i32
-   (BINARY_AND_i32
-(LLO GPRI64:$src),
-    (LOADCONST_i32 0xFFFFFFFF))
-  ) >;
-
-
 def actos_v2i16:Pat < (v2i16 (anyext GPRV2I8:$src)),
 (IL_ASV2SHORT_v2i32
 (USHRVEC_v2i32
@@ -589,21 +472,6 @@ def uctof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I8:$src)),
   (VCREATE_v2i32 (LOADCONST_i32 24))))) >;


-def ftosc_v2i8:Pat < (v2i8 (fp_to_sint GPRV2F32:$src)),
-(v2i8
- (IL_ASV2CHAR_v2i32
-  (BINARY_AND_v2i32
-(FTOI_v2i32 GPRV2F32:$src),
-   (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >;
-
-
-def ftouc_v2i8:Pat < (v2i8 (fp_to_uint GPRV2F32:$src)),
-(v2i8
- (IL_ASV2CHAR_v2i32
-  (BINARY_AND_v2i32
-(FTOU_v2i32 GPRV2F32:$src),
-   (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >;
-
 def sctod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I8:$src)),
 (v2f64 
 (VINSERT_v2f64
@@ -656,29 +524,6 @@ def uctod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I8:$src)),
  ), 1, 256)
 ) >;

-
-def dtosc_v2i8:Pat < (v2i8 (fp_to_sint GPRV2F64:$src)),
-(v2i8
- (IL_ASV2CHAR_v2i32
-  (BINARY_AND_v2i32
-(FTOI_v2i32 (VINSERT_v2f32 
-             (VCREATE_v2f32 
-              (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))),
-             (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)),
-   (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >;
-
-
-def dtouc_v2i8:Pat < (v2i8 (fp_to_uint GPRV2F64:$src)),
-(v2i8
- (IL_ASV2CHAR_v2i32
-  (BINARY_AND_v2i32
-(FTOU_v2i32 (VINSERT_v2f32 
-             (VCREATE_v2f32 
-              (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))),
-             (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)),
-   (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >;
-
-
 def sstof_v2f32:Pat < (v2f32 (sint_to_fp GPRV2I16:$src)),
 (v2f32
 (ITOF_v2f32
@@ -699,22 +544,6 @@ def ustof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I16:$src)),
   (VCREATE_v2i32 (LOADCONST_i32 16))))) >;


-def ftoss_v2i16:Pat < (v2i16 (fp_to_sint GPRV2F32:$src)),
-(v2i16
- (IL_ASV2SHORT_v2i32
-  (BINARY_AND_v2i32
-(FTOI_v2i32 GPRV2F32:$src),
-   (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-
-def ftous_v2i16:Pat < (v2i16 (fp_to_uint GPRV2F32:$src)),
-(v2i16
- (IL_ASV2SHORT_v2i32
-  (BINARY_AND_v2i32
-(FTOU_v2i32 GPRV2F32:$src),
-   (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-
 def sstod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I16:$src)),
 (v2f64 
 (VINSERT_v2f64
@@ -768,77 +597,6 @@ def ustod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I16:$src)),
 ) >;


-def dtoss_v2i16:Pat < (v2i16 (fp_to_sint GPRV2F64:$src)),
-(v2i16
- (IL_ASV2SHORT_v2i32
-  (BINARY_AND_v2i32
-(FTOI_v2i32 (VINSERT_v2f32 
-             (VCREATE_v2f32 
-              (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))),
-             (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)),
-   (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-
-def dtous_v2i16:Pat < (v2i16 (fp_to_uint GPRV2F64:$src)),
-(v2i16
- (IL_ASV2SHORT_v2i32
-  (BINARY_AND_v2i32
-(FTOU_v2i32 (VINSERT_v2f32 
-             (VCREATE_v2f32 
-              (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))),
-             (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)),
-   (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-def stoc_v2i8:Pat < (v2i8 (trunc GPRV2I16:$src)),
-(IL_ASV2CHAR_v2i32
-   (IL_ASV2INT_v2i16
-(BINARY_AND_v2i16 GPRV2I16:$src,
-     (VCREATE_v2i16 (LOADCONST_i16 0x000000FF))))
-  ) >;
-
-
-def itoc_v2i8:Pat < (v2i8 (trunc GPRV2I32:$src)),
-(IL_ASV2CHAR_v2i32
-   (IL_ASV2INT_v2i32
-(BINARY_AND_v2i32 GPRV2I32:$src,
-     (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))
-  ) >;
-
-
-def itos_v2i16:Pat < (v2i16 (trunc GPRV2I32:$src)),
-(IL_ASV2SHORT_v2i32
-   (IL_ASV2INT_v2i32
-(BINARY_AND_v2i32 GPRV2I32:$src,
-     (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))
-  ) >;
-
-
-def ltoc_v2i8:Pat < (v2i8 (trunc GPRV2I64:$src)),
-(IL_ASV2CHAR_v2i32
-   (BINARY_AND_v2i32
-(LLO_v2i64 GPRV2I64:$src),
-    (VCREATE_v2i32 (LOADCONST_i32 0x000000FF)))
-  ) >;
-
-
-def ltos_v2i16:Pat < (v2i16 (trunc GPRV2I64:$src)),
-(IL_ASV2SHORT_v2i32
-   (BINARY_AND_v2i32
-(LLO_v2i64 GPRV2I64:$src),
-    (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF)))
-  ) >;
-
-
-def ltoi_v2i32:Pat < (v2i32 (trunc GPRV2I64:$src)),
-(IL_ASV2INT_v2i32
-   (BINARY_AND_v2i32
-(LLO_v2i64 GPRV2I64:$src),
-    (VCREATE_v2i32 (LOADCONST_i32 0xFFFFFFFF)))
-  ) >;
-
-
-
-
 def actos_v4i16:Pat < (v4i16 (anyext GPRV4I8:$src)),
 (IL_ASV4SHORT_v4i32
 (USHRVEC_v4i32
@@ -941,22 +699,6 @@ def uctof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I8:$src)),
   (VCREATE_v4i32 (LOADCONST_i32 24))))) >;


-def ftosc_v4i8:Pat < (v4i8 (fp_to_sint GPRV4F32:$src)),
-(v4i8
- (IL_ASV4CHAR_v4i32
-  (BINARY_AND_v4i32
-(FTOI_v4i32 GPRV4F32:$src),
-   (VCREATE_v4i32 (LOADCONST_i32 0x000000FF))))) >;
-
-
-def ftouc_v4i8:Pat < (v4i8 (fp_to_uint GPRV4F32:$src)),
-(v4i8
- (IL_ASV4CHAR_v4i32
-  (BINARY_AND_v4i32
-(FTOU_v4i32 GPRV4F32:$src),
-   (VCREATE_v4i32 (LOADCONST_i32 0x000000FF))))) >;
-
-
 def sstof_v4f32:Pat < (v4f32 (sint_to_fp GPRV4I16:$src)),
 (v4f32
 (ITOF_v4f32
@@ -976,47 +718,3 @@ def ustof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I16:$src)),
    (VCREATE_v4i32 (LOADCONST_i32 16))),
   (VCREATE_v4i32 (LOADCONST_i32 16))))) >;

-
-def ftoss_v4i16:Pat < (v4i16 (fp_to_sint GPRV4F32:$src)),
-(v4i16
- (IL_ASV4SHORT_v4i32
-  (BINARY_AND_v4i32
-(FTOI_v4i32 GPRV4F32:$src),
-   (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-
-def ftous_v4i16:Pat < (v4i16 (fp_to_uint GPRV4F32:$src)),
-(v4i16
- (IL_ASV4SHORT_v4i32
-  (BINARY_AND_v4i32
-(FTOU_v4i32 GPRV4F32:$src),
-   (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF))))) >;
-
-
-
-
-
-def stoc_v4i8:Pat < (v4i8 (trunc GPRV4I16:$src)),
-(IL_ASV4CHAR_v4i32
-   (IL_ASV4INT_v4i16
-(BINARY_AND_v4i16 GPRV4I16:$src,
-     (VCREATE_v4i16 (LOADCONST_i16 0x000000FF))))
-  ) >;
-
-
-def itoc_v4i8:Pat < (v4i8 (trunc GPRV4I32:$src)),
-(IL_ASV4CHAR_v4i32
-   (IL_ASV4INT_v4i32
-(BINARY_AND_v4i32 GPRV4I32:$src,
-     (VCREATE_v4i32 (LOADCONST_i32 0x000000FF))))
-  ) >;
-
-
-def itos_v4i16:Pat < (v4i16 (trunc GPRV4I32:$src)),
-(IL_ASV4SHORT_v4i32
-   (IL_ASV4INT_v4i32
-(BINARY_AND_v4i32 GPRV4I32:$src,
-     (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF))))
-  ) >;
-
-
@@ -701,7 +701,6 @@ AMDILTargetLowering::convertToReg(MachineOperand op) const
    setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
    setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
    setOperationAction(ISD::FP_ROUND, VT, Expand);
-    setOperationAction(ISD::OR, VT, Custom);
    setOperationAction(ISD::SUBE, VT, Expand);
    setOperationAction(ISD::SUBC, VT, Expand);
    setOperationAction(ISD::ADD, VT, Custom);
@@ -1599,10 +1598,7 @@ AMDILTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
      LOWER(EXTRACT_SUBVECTOR);
      LOWER(SCALAR_TO_VECTOR);
      LOWER(CONCAT_VECTORS);
-      LOWER(AND);
-      LOWER(OR);
      LOWER(SELECT);
-      LOWER(SELECT_CC);
      LOWER(SETCC);
      LOWER(SIGN_EXTEND_INREG);
      LOWER(BITCAST);
@@ -3565,29 +3561,6 @@ AMDILTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
  return Res;
 }
 SDValue
-AMDILTargetLowering::LowerAND(SDValue Op, SelectionDAG &DAG) const
-{
-  SDValue andOp;
-  andOp = DAG.getNode(
-      AMDILISD::AND,
-      Op.getDebugLoc(),
-      Op.getValueType(),
-      Op.getOperand(0),
-      Op.getOperand(1));
-  return andOp;
-}
-SDValue
-AMDILTargetLowering::LowerOR(SDValue Op, SelectionDAG &DAG) const
-{
-  SDValue orOp;
-  orOp = DAG.getNode(AMDILISD::OR,
-      Op.getDebugLoc(),
-      Op.getValueType(),
-      Op.getOperand(0),
-      Op.getOperand(1));
-  return orOp;
-}
-SDValue
 AMDILTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const
 {
  SDValue Cond = Op.getOperand(0);
@@ -3601,60 +3574,6 @@ AMDILTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const
  return Cond;
 }
 SDValue
-AMDILTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
-{
-  SDValue Cond;
-  SDValue LHS = Op.getOperand(0);
-  SDValue RHS = Op.getOperand(1);
-  SDValue TRUE = Op.getOperand(2);
-  SDValue FALSE = Op.getOperand(3);
-  SDValue CC = Op.getOperand(4);
-  DebugLoc DL = Op.getDebugLoc();
-  bool skipCMov = false;
-  bool genINot = false;
-  EVT OVT = Op.getValueType();
-
-  // Check for possible elimination of cmov
-  if (TRUE.getValueType().getSimpleVT().SimpleTy == MVT::i32) {
-    const ConstantSDNode *trueConst
-      = dyn_cast<ConstantSDNode>( TRUE.getNode() );
-    const ConstantSDNode *falseConst
-      = dyn_cast<ConstantSDNode>( FALSE.getNode() );
-    if (trueConst && falseConst) {
-      // both possible result values are constants
-      if (trueConst->isAllOnesValue()
-          && falseConst->isNullValue()) { // and convenient constants
-        skipCMov = true;
-      }
-      else if (trueConst->isNullValue()
-          && falseConst->isAllOnesValue()) { // less convenient
-        skipCMov = true;
-        genINot = true;
-      }
-    }
-  }
-  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
-  unsigned int AMDILCC = CondCCodeToCC(
-      SetCCOpcode,
-      LHS.getValueType().getSimpleVT().SimpleTy);
-  assert((AMDILCC != AMDILCC::COND_ERROR) && "Invalid SetCC!");
-  Cond = DAG.getNode(
-      AMDILISD::CMP,
-      DL,
-      LHS.getValueType(),
-      DAG.getConstant(AMDILCC, MVT::i32),
-      LHS,
-      RHS);
-  Cond = getConversionNode(DAG, Cond, Op, true);
-  if (genINot) {
-    Cond = DAG.getNode(AMDILISD::NOT, DL, OVT, Cond);
-  }
-  if (!skipCMov) {
-    Cond = DAG.getNode(AMDILISD::CMOVLOG, DL, OVT, Cond, TRUE, FALSE);
-  }
-  return Cond;
-}
-SDValue
 AMDILTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const
 {
  SDValue Cond;
@@ -13,9 +13,6 @@
 //===--------------------------------------------------------------------===//
 // Custom patterns for conversion operations
 //===--------------------------------------------------------------------===////
-// Pattern to remap integer or to IL_or
-def : Pat<(i32 (or GPRI32:$src0, GPRI32:$src1)),
-          (i32 (BINARY_OR_i32 GPRI32:$src0, GPRI32:$src1))>;
 // float ==> long patterns
 // unsigned: f32 -> i64
 def FTOUL : Pat<(i64 (fp_to_uint GPRF32:$src)),
@@ -14,11 +14,6 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
  defm MOVE       : UnaryOpMC<IL_OP_MOV, IL_mov>;
  defm PHIMOVE    : UnaryOpMC<IL_OP_MOV, IL_phimov>;
 }
-defm BINARY_NOT : UnaryOpMC<IL_OP_I_NOT, IL_not>;
-defm BINARY_OR  : BinaryOpMC<IL_OP_I_OR, IL_or>;
-defm BINARY_AND : BinaryOpMC<IL_OP_AND, IL_and>;
-defm BINARY_XOR : BinaryOpMC<IL_OP_I_XOR, IL_xor>;
-defm AND        : BinaryOpMCInt<IL_OP_AND, and>;
 defm CMOV       : BinaryOpMC<IL_OP_CMOV, IL_cmov>;
 defm DIV_INF    : BinaryOpMC<IL_OP_DIV_INF, IL_div_inf>;
 defm SMAX       : BinaryOpMCInt<IL_OP_I_MAX, IL_smax>;
@@ -63,7 +58,6 @@ defm SHR        : BinaryOpMCi32Const<IL_OP_I_SHR, sra>;
 defm SHLVEC     : BinaryOpMCi32<IL_OP_I_SHL, shl>;
 defm SHRVEC     : BinaryOpMCi32<IL_OP_I_SHR, sra>;
 defm ADD        : BinaryOpMCi32<IL_OP_I_ADD, add>;
-defm CUSTOM_XOR : BinaryOpMCInt<IL_OP_I_XOR, xor>;
 // get rid of the addri via the tablegen instead of custom lowered instruction
 defm CUSTOM_ADD : BinaryOpMCi32<IL_OP_I_ADD, IL_add>;
 defm EADD   : BinaryOpMCi32<IL_OP_I_ADD, adde>;
@@ -67,8 +67,6 @@ unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
    default: return AMDGPUInstrInfo::getISAOpcode(opcode);
    case AMDIL::CUSTOM_ADD_i32:
      return AMDIL::ADD_INT;
-    case AMDIL::CUSTOM_XOR_i32:
-      return AMDIL::XOR_INT;
    case AMDIL::IEQ:
      return AMDIL::SETE_INT;
    case AMDIL::INE:
@@ -390,26 +390,23 @@ def KILLGT : R600_2OP <

 def AND_INT : R600_2OP <
  0x30, "AND_INT",
-  []> {
-  let AMDILOp = AMDILInst.AND_i32;
-}
+  [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
+>;

 def OR_INT : R600_2OP <
  0x31, "OR_INT",
-  []>{
-  let AMDILOp = AMDILInst.BINARY_OR_i32;
-}
+  [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
+>;

 def XOR_INT : R600_2OP <
  0x32, "XOR_INT",
-  []
+  [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 >;

 def NOT_INT : R600_1OP <
  0x33, "NOT_INT",
-  []>{
-  let AMDILOp = AMDILInst.BINARY_NOT_i32;
-}
+  [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
+>;

 def ADD_INT : R600_2OP <
  0x34, "ADD_INT",
@@ -98,22 +98,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
                .addOperand(MI.getOperand(1));
        break;

-      case AMDIL::BINARY_OR_f32:
-        {
-        unsigned tmp0 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
-        BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::FTOI), tmp0)
-                .addOperand(MI.getOperand(1));
-        unsigned tmp1 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
-        BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::FTOI), tmp1)
-                .addOperand(MI.getOperand(2));
-        unsigned tmp2 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
-        BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::BINARY_OR_i32), tmp2)
-                .addReg(tmp0)
-                .addReg(tmp1);
-        BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::ITOF), MI.getOperand(0).getReg())
-                .addReg(tmp2);
-        break;
-        }
      case AMDIL::CLAMP_f32:
        {
          MachineOperand lowOp = MI.getOperand(2);