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i965: Use immediate storage in inherited brw_reg.

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Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner
2015-10-24 14:55:57 -07:00
parent d74dd703f8
commit 1392e45bfb
10 changed files with 96 additions and 95 deletions
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src/mesa/drivers/dri/i965/brw_fs.cpp
+40 -40
View File
@@ -379,7 +379,7 @@ fs_reg::fs_reg(float f)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->stride = 0;
this->fixed_hw_reg.f = f;
this->f = f;
}
/** Immediate value constructor. */
@@ -389,7 +389,7 @@ fs_reg::fs_reg(int32_t i)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->stride = 0;
this->fixed_hw_reg.d = i;
this->d = i;
}
/** Immediate value constructor. */
@@ -399,7 +399,7 @@ fs_reg::fs_reg(uint32_t u)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->stride = 0;
this->fixed_hw_reg.ud = u;
this->ud = u;
}
/** Vector float immediate value constructor. */
@@ -408,7 +408,7 @@ fs_reg::fs_reg(uint8_t vf[4])
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->fixed_hw_reg.ud, vf, sizeof(unsigned));
memcpy(&this->ud, vf, sizeof(unsigned));
}
/** Vector float immediate value constructor. */
@@ -417,7 +417,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->fixed_hw_reg.ud = (vf0 << 0) |
this->ud = (vf0 << 0) |
(vf1 << 8) |
(vf2 << 16) |
(vf3 << 24);
@@ -443,9 +443,10 @@ fs_reg::equals(const fs_reg &r) const
negate == r.negate &&
abs == r.abs &&
!reladdr && !r.reladdr &&
((file != HW_REG && file != IMM) ||
(file != HW_REG ||
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0) &&
(file != IMM || d == r.d) &&
stride == r.stride);
}
@@ -719,7 +720,7 @@ fs_inst::components_read(unsigned i) const
assert(src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
/* First/second FB write color. */
if (i < 2)
return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.ud;
return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
else
return 1;
@@ -739,10 +740,10 @@ fs_inst::components_read(unsigned i) const
assert(src[8].file == IMM && src[9].file == IMM);
/* Texture coordinates. */
if (i == 0)
return src[8].fixed_hw_reg.ud;
return src[8].ud;
/* Texture derivatives. */
else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL)
return src[9].fixed_hw_reg.ud;
return src[9].ud;
/* Texture offset. */
else if (i == 7)
return 2;
@@ -757,7 +758,7 @@ fs_inst::components_read(unsigned i) const
assert(src[3].file == IMM);
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.ud;
return src[3].ud;
/* Surface operation source (ignored for reads). */
else if (i == 1)
return 0;
@@ -770,10 +771,10 @@ fs_inst::components_read(unsigned i) const
src[4].file == IMM);
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.ud;
return src[3].ud;
/* Surface operation source. */
else if (i == 1)
return src[4].fixed_hw_reg.ud;
return src[4].ud;
else
return 1;
@@ -781,10 +782,10 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: {
assert(src[3].file == IMM &&
src[4].file == IMM);
const unsigned op = src[4].fixed_hw_reg.ud;
const unsigned op = src[4].ud;
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.ud;
return src[3].ud;
/* Surface operation source. */
else if (i == 1 && op == BRW_AOP_CMPWR)
return 2;
@@ -1666,11 +1667,11 @@ fs_visitor::assign_gs_urb_setup()
if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8) {
assert(inst->src[0].file == IMM);
inst->src[0] = retype(brw_vec8_grf(first_icp_handle +
inst->src[0].fixed_hw_reg.ud,
inst->src[0].ud,
0), BRW_REGISTER_TYPE_UD);
/* for now, assume constant - we can do per-slot offsets later */
assert(inst->src[1].file == IMM);
inst->offset = inst->src[1].fixed_hw_reg.ud;
inst->offset = inst->src[1].ud;
inst->src[1] = fs_reg();
inst->mlen = 1;
inst->base_mrf = -1;
@@ -2071,8 +2072,7 @@ fs_visitor::opt_algebraic()
if (inst->dst.type != inst->src[0].type)
assert(!"unimplemented: saturate mixed types");
if (brw_saturate_immediate(inst->dst.type,
&inst->src[0].fixed_hw_reg)) {
if (brw_saturate_immediate(inst->dst.type, &inst->src[0])) {
inst->saturate = false;
progress = true;
}
@@ -2112,7 +2112,7 @@ fs_visitor::opt_algebraic()
if (inst->src[0].file == IMM) {
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
inst->opcode = BRW_OPCODE_MOV;
inst->src[0].fixed_hw_reg.f *= inst->src[1].fixed_hw_reg.f;
inst->src[0].f *= inst->src[1].f;
inst->src[1] = reg_undef;
progress = true;
break;
@@ -2133,7 +2133,7 @@ fs_visitor::opt_algebraic()
if (inst->src[0].file == IMM) {
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
inst->opcode = BRW_OPCODE_MOV;
inst->src[0].fixed_hw_reg.f += inst->src[1].fixed_hw_reg.f;
inst->src[0].f += inst->src[1].f;
inst->src[1] = reg_undef;
progress = true;
break;
@@ -2182,7 +2182,7 @@ fs_visitor::opt_algebraic()
case BRW_CONDITIONAL_L:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
if (inst->src[1].fixed_hw_reg.f >= 1.0f) {
if (inst->src[1].f >= 1.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[1] = reg_undef;
inst->conditional_mod = BRW_CONDITIONAL_NONE;
@@ -2197,7 +2197,7 @@ fs_visitor::opt_algebraic()
case BRW_CONDITIONAL_G:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
if (inst->src[1].fixed_hw_reg.f <= 0.0f) {
if (inst->src[1].f <= 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[1] = reg_undef;
inst->conditional_mod = BRW_CONDITIONAL_NONE;
@@ -2234,7 +2234,7 @@ fs_visitor::opt_algebraic()
progress = true;
} else if (inst->src[1].file == IMM && inst->src[2].file == IMM) {
inst->opcode = BRW_OPCODE_ADD;
inst->src[1].fixed_hw_reg.f *= inst->src[2].fixed_hw_reg.f;
inst->src[1].f *= inst->src[2].f;
inst->src[2] = reg_undef;
progress = true;
}
@@ -2259,7 +2259,7 @@ fs_visitor::opt_algebraic()
} else if (inst->src[1].file == IMM) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = component(inst->src[0],
inst->src[1].fixed_hw_reg.ud);
inst->src[1].ud);
inst->sources = 1;
inst->force_writemask_all = true;
progress = true;
@@ -3081,7 +3081,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
fs_reg const_offset_reg = inst->src[1];
assert(const_offset_reg.file == IMM &&
const_offset_reg.type == BRW_REGISTER_TYPE_UD);
const_offset_reg.fixed_hw_reg.ud /= 4;
const_offset_reg.ud /= 4;
fs_reg payload, offset;
if (devinfo->gen >= 9) {
@@ -3250,7 +3250,7 @@ fs_visitor::lower_integer_multiplication()
continue;
if (inst->src[1].file == IMM &&
inst->src[1].fixed_hw_reg.ud < (1 << 16)) {
inst->src[1].ud < (1 << 16)) {
/* The MUL instruction isn't commutative. On Gen <= 6, only the low
* 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
* src1 are used.
@@ -3326,8 +3326,8 @@ fs_visitor::lower_integer_multiplication()
fs_reg src1_1_w = inst->src[1];
if (inst->src[1].file == IMM) {
src1_0_w.fixed_hw_reg.ud &= 0xffff;
src1_1_w.fixed_hw_reg.ud >>= 16;
src1_0_w.ud &= 0xffff;
src1_1_w.ud >>= 16;
} else {
src1_0_w.type = BRW_REGISTER_TYPE_UW;
if (src1_0_w.stride != 0) {
@@ -3482,7 +3482,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
const fs_reg &src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL];
fs_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK];
const unsigned components =
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.ud;
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
/* We can potentially have a message length of up to 15, so we have to set
* base_mrf to either 0 or 1 in order to fit in m0..m15.
@@ -3822,7 +3822,7 @@ is_high_sampler(const struct brw_device_info *devinfo, const fs_reg &sampler)
if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.ud >= 16;
return sampler.file != IMM || sampler.ud >= 16;
}
static void
@@ -4057,8 +4057,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
const fs_reg &sampler = inst->src[6];
const fs_reg &offset_value = inst->src[7];
assert(inst->src[8].file == IMM && inst->src[9].file == IMM);
const unsigned coord_components = inst->src[8].fixed_hw_reg.ud;
const unsigned grad_components = inst->src[9].fixed_hw_reg.ud;
const unsigned coord_components = inst->src[8].ud;
const unsigned grad_components = inst->src[9].ud;
if (devinfo->gen >= 7) {
lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
@@ -4384,7 +4384,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
* circumstances it can end up with a message that is too long in SIMD16
* mode.
*/
const unsigned coord_components = inst->src[8].fixed_hw_reg.ud;
const unsigned coord_components = inst->src[8].ud;
/* First three arguments are the sample index and the two arguments for
* the MCS data.
*/
@@ -4692,22 +4692,22 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
fprintf(file, "%ff", inst->src[i].fixed_hw_reg.f);
fprintf(file, "%ff", inst->src[i].f);
break;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_D:
fprintf(file, "%dd", inst->src[i].fixed_hw_reg.d);
fprintf(file, "%dd", inst->src[i].d);
break;
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_UD:
fprintf(file, "%uu", inst->src[i].fixed_hw_reg.ud);
fprintf(file, "%uu", inst->src[i].ud);
break;
case BRW_REGISTER_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 24) & 0xff));
brw_vf_to_float((inst->src[i].ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 24) & 0xff));
break;
default:
fprintf(file, "???");
src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
+3 -3
View File
@@ -219,7 +219,7 @@ fs_visitor::opt_combine_constants()
inst->src[i].type != BRW_REGISTER_TYPE_F)
continue;
float val = fabsf(inst->src[i].fixed_hw_reg.f);
float val = fabsf(inst->src[i].f);
struct imm *imm = find_imm(&table, val);
if (imm) {
@@ -299,9 +299,9 @@ fs_visitor::opt_combine_constants()
reg->reg = table.imm[i].reg;
reg->subreg_offset = table.imm[i].subreg_offset;
reg->stride = 0;
reg->negate = signbit(reg->fixed_hw_reg.f) !=
reg->negate = signbit(reg->f) !=
signbit(table.imm[i].val);
assert(fabsf(reg->fixed_hw_reg.f) == table.imm[i].val);
assert(fabsf(reg->f) == table.imm[i].val);
}
}
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+6 -6
View File
@@ -369,8 +369,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
switch(inst->opcode) {
case BRW_OPCODE_SEL:
if (inst->src[1].file != IMM ||
inst->src[1].fixed_hw_reg.f < 0.0 ||
inst->src[1].fixed_hw_reg.f > 1.0) {
inst->src[1].f < 0.0 ||
inst->src[1].f > 1.0) {
return false;
}
break;
@@ -477,14 +477,14 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
if (inst->src[i].abs) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(val.type, &val.fixed_hw_reg)) {
!brw_abs_immediate(val.type, &val)) {
continue;
}
}
if (inst->src[i].negate) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(val.type, &val.fixed_hw_reg)) {
!brw_negate_immediate(val.type, &val)) {
continue;
}
}
@@ -605,10 +605,10 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
* anyway.
*/
assert(i == 0);
if (inst->src[0].fixed_hw_reg.f != 0.0f) {
if (inst->src[0].f != 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = val;
inst->src[0].fixed_hw_reg.f = 1.0f / inst->src[0].fixed_hw_reg.f;
inst->src[0].f = 1.0f / inst->src[0].f;
progress = true;
}
break;
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+8 -8
View File
@@ -110,20 +110,20 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
(xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
} else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
bool xs0_negate = xs[0].negate;
bool xs1_negate = xs[1].file == IMM ? xs[1].fixed_hw_reg.f < 0.0f
bool xs1_negate = xs[1].file == IMM ? xs[1].f < 0.0f
: xs[1].negate;
bool ys0_negate = ys[0].negate;
bool ys1_negate = ys[1].file == IMM ? ys[1].fixed_hw_reg.f < 0.0f
bool ys1_negate = ys[1].file == IMM ? ys[1].f < 0.0f
: ys[1].negate;
float xs1_imm = xs[1].fixed_hw_reg.f;
float ys1_imm = ys[1].fixed_hw_reg.f;
float xs1_imm = xs[1].f;
float ys1_imm = ys[1].f;
xs[0].negate = false;
xs[1].negate = false;
ys[0].negate = false;
ys[1].negate = false;
xs[1].fixed_hw_reg.f = fabsf(xs[1].fixed_hw_reg.f);
ys[1].fixed_hw_reg.f = fabsf(ys[1].fixed_hw_reg.f);
xs[1].f = fabsf(xs[1].f);
ys[1].f = fabsf(ys[1].f);
bool ret = (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
(xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
@@ -132,8 +132,8 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
xs[1].negate = xs[1].file == IMM ? false : xs1_negate;
ys[0].negate = ys0_negate;
ys[1].negate = ys[1].file == IMM ? false : ys1_negate;
xs[1].fixed_hw_reg.f = xs1_imm;
ys[1].fixed_hw_reg.f = ys1_imm;
xs[1].f = xs1_imm;
ys[1].f = ys1_imm;
*negate = (xs0_negate != xs1_negate) != (ys0_negate != ys1_negate);
return ret;
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+6 -6
View File
@@ -92,22 +92,22 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
switch (reg->type) {
case BRW_REGISTER_TYPE_F:
brw_reg = brw_imm_f(reg->fixed_hw_reg.f);
brw_reg = brw_imm_f(reg->f);
break;
case BRW_REGISTER_TYPE_D:
brw_reg = brw_imm_d(reg->fixed_hw_reg.d);
brw_reg = brw_imm_d(reg->d);
break;
case BRW_REGISTER_TYPE_UD:
brw_reg = brw_imm_ud(reg->fixed_hw_reg.ud);
brw_reg = brw_imm_ud(reg->ud);
break;
case BRW_REGISTER_TYPE_W:
brw_reg = brw_imm_w(reg->fixed_hw_reg.d);
brw_reg = brw_imm_w(reg->d);
break;
case BRW_REGISTER_TYPE_UW:
brw_reg = brw_imm_uw(reg->fixed_hw_reg.ud);
brw_reg = brw_imm_uw(reg->ud);
break;
case BRW_REGISTER_TYPE_VF:
brw_reg = brw_imm_vf(reg->fixed_hw_reg.ud);
brw_reg = brw_imm_vf(reg->ud);
break;
default:
unreachable("not reached");
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+2 -2
View File
@@ -322,7 +322,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
inst->shadow_compare = true;
if (offset_value.file == IMM)
inst->offset = offset_value.fixed_hw_reg.ud;
inst->offset = offset_value.ud;
if (op == ir_tg4) {
inst->offset |=
@@ -949,7 +949,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
fs_reg offset;
if (gs_vertex_count.file == IMM) {
per_slot_offsets = fs_reg(output_vertex_size_owords *
gs_vertex_count.fixed_hw_reg.ud);
gs_vertex_count.ud);
} else {
per_slot_offsets = vgrf(glsl_type::int_type);
bld.MUL(per_slot_offsets, gs_vertex_count,
src/mesa/drivers/dri/i965/brw_shader.cpp
+5 -5
View File
@@ -700,7 +700,7 @@ backend_reg::is_zero() const
if (file != IMM)
return false;
return fixed_hw_reg.d == 0;
return d == 0;
}
bool
@@ -710,8 +710,8 @@ backend_reg::is_one() const
return false;
return type == BRW_REGISTER_TYPE_F
? fixed_hw_reg.f == 1.0
: fixed_hw_reg.d == 1;
? f == 1.0
: d == 1;
}
bool
@@ -722,9 +722,9 @@ backend_reg::is_negative_one() const
switch (type) {
case BRW_REGISTER_TYPE_F:
return fixed_hw_reg.f == -1.0;
return f == -1.0;
case BRW_REGISTER_TYPE_D:
return fixed_hw_reg.d == -1;
return d == -1;
default:
return false;
}
src/mesa/drivers/dri/i965/brw_vec4.cpp
+20 -19
View File
@@ -77,7 +77,7 @@ src_reg::src_reg(float f)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->fixed_hw_reg.f = f;
this->f = f;
}
src_reg::src_reg(uint32_t u)
@@ -86,7 +86,7 @@ src_reg::src_reg(uint32_t u)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->fixed_hw_reg.ud = u;
this->ud = u;
}
src_reg::src_reg(int32_t i)
@@ -95,7 +95,7 @@ src_reg::src_reg(int32_t i)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->fixed_hw_reg.d = i;
this->d = i;
}
src_reg::src_reg(uint8_t vf[4])
@@ -104,7 +104,7 @@ src_reg::src_reg(uint8_t vf[4])
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->fixed_hw_reg.ud, vf, sizeof(unsigned));
memcpy(&this->ud, vf, sizeof(unsigned));
}
src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
@@ -113,7 +113,7 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->fixed_hw_reg.ud = (vf0 << 0) |
this->ud = (vf0 << 0) |
(vf1 << 8) |
(vf2 << 16) |
(vf3 << 24);
@@ -218,7 +218,7 @@ dst_reg::equals(const dst_reg &r) const
writemask == r.writemask &&
(reladdr == r.reladdr ||
(reladdr && r.reladdr && reladdr->equals(*r.reladdr))) &&
((file != HW_REG && file != IMM) ||
(file != HW_REG ||
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0));
}
@@ -363,8 +363,10 @@ src_reg::equals(const src_reg &r) const
abs == r.abs &&
swizzle == r.swizzle &&
!reladdr && !r.reladdr &&
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0);
(file != HW_REG ||
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0) &&
(file != IMM || d == r.d));
}
bool
@@ -397,7 +399,7 @@ vec4_visitor::opt_vector_float()
inst->src[0].file != IMM)
continue;
int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.f);
int vf = brw_float_to_vf(inst->src[0].f);
if (vf == -1)
continue;
@@ -660,8 +662,7 @@ vec4_visitor::opt_algebraic()
if (inst->dst.type != inst->src[0].type)
assert(!"unimplemented: saturate mixed types");
if (brw_saturate_immediate(inst->dst.type,
&inst->src[0].fixed_hw_reg)) {
if (brw_saturate_immediate(inst->dst.type, &inst->src[0])) {
inst->saturate = false;
progress = true;
}
@@ -1467,20 +1468,20 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
fprintf(file, "%fF", inst->src[i].fixed_hw_reg.f);
fprintf(file, "%fF", inst->src[i].f);
break;
case BRW_REGISTER_TYPE_D:
fprintf(file, "%dD", inst->src[i].fixed_hw_reg.d);
fprintf(file, "%dD", inst->src[i].d);
break;
case BRW_REGISTER_TYPE_UD:
fprintf(file, "%uU", inst->src[i].fixed_hw_reg.ud);
fprintf(file, "%uU", inst->src[i].ud);
break;
case BRW_REGISTER_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 24) & 0xff));
brw_vf_to_float((inst->src[i].ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].ud >> 24) & 0xff));
break;
default:
fprintf(file, "???");
@@ -1817,7 +1818,7 @@ vec4_visitor::convert_to_hw_regs()
case IMM:
reg = brw_imm_reg(src.type);
reg.ud = src.fixed_hw_reg.ud;
reg.ud = src.ud;
break;
case UNIFORM:
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+5 -5
View File
@@ -134,20 +134,20 @@ try_constant_propagate(const struct brw_device_info *devinfo,
if (inst->src[arg].abs) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
!brw_abs_immediate(value.type, &value)) {
return false;
}
}
if (inst->src[arg].negate) {
if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
!brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
!brw_negate_immediate(value.type, &value)) {
return false;
}
}
if (value.type == BRW_REGISTER_TYPE_VF)
value.fixed_hw_reg.ud = swizzle_vf_imm(value.fixed_hw_reg.ud,
value.ud = swizzle_vf_imm(value.ud,
inst->src[arg].swizzle);
switch (inst->opcode) {
@@ -359,8 +359,8 @@ try_copy_propagate(const struct brw_device_info *devinfo,
inst->src[0].type != BRW_REGISTER_TYPE_F ||
inst->src[1].file != IMM ||
inst->src[1].type != BRW_REGISTER_TYPE_F ||
inst->src[1].fixed_hw_reg.f < 0.0 ||
inst->src[1].fixed_hw_reg.f > 1.0) {
inst->src[1].f < 0.0 ||
inst->src[1].f > 1.0) {
return false;
}
if (!inst->saturate)
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+1 -1
View File
@@ -863,7 +863,7 @@ vec4_visitor::is_high_sampler(src_reg sampler)
if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.ud >= 16;
return sampler.file != IMM || sampler.ud >= 16;
}
void