etnaviv: isa: Add "thread" info to TEX instruction
Blob generates this with the glmark2:texture benchmark on STM32MP257. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38363>
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@@ -11,7 +11,7 @@ SPDX-License-Identifier: MIT
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</template>
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<template name="INSTR_TEX">
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{NAME}
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{NAME}{THREAD}
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</template>
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<template name="INSTR_CF">
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@@ -700,8 +700,13 @@ SPDX-License-Identifier: MIT
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<field name="RMODE" low="32" high="34" type="#reg_addressing_mode"/>
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<field name="TEX_SWIZ" low="35" high="42" type="#src-swizzle"/>
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<pattern pos="109">0</pattern>
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<pattern pos="120">0</pattern>
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<field name="LOW_HALF" pos="109" type="bool"/>
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<field name="HIGH_HALF" pos="120" type="bool"/>
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<derived name="THREAD" type="#thread">
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<expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr>
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</derived>
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<pattern pos="127">0</pattern>
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</bitset>
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@@ -365,6 +365,17 @@ INSTANTIATE_TEST_SUITE_P(texldgpcf, DisasmTest,
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);
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// clang-format on
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// clang-format off
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INSTANTIATE_TEST_SUITE_P(texldthreaded, DisasmTest,
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testing::Values(
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// taken from "glmark2 -b texture:texture-filter=linear (GC8000)
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disasm_state{ {0x07831018, 0x15001f20, 0x00000020, 0x00002000}, "texld.t0 t3, tex0.xyzw, th1.xyyy, void, void\n"},
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disasm_state{ {0x07831018, 0x3f801f20, 0x00000020, 0x01000000}, "texld.t1 t3, tex0.xyzw, th1.zwww, void, void\n"},
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disasm_state{ {0x07811003, 0x39003805, 0x01c80140, 0x00000000}, "mul.rtz t1, t3.xyzw, t2.xyzw, void\n"}
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)
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);
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// clang-format on
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// clang-format off
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INSTANTIATE_TEST_SUITE_P(LoadStoreVariants, DisasmTest,
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testing::Values(
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