agx: Split off NIR preprocessing from compiling
So we can specialize after lowering I/O. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
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@@ -1883,24 +1883,13 @@ agx_compile_function_nir(nir_shader *nir, nir_function_impl *impl,
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return offset;
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}
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/*
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* Preprocess NIR. In particular, this lowers I/O. Drivers should call this
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* as soon as they don't need unlowered I/O.
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*/
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void
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agx_compile_shader_nir(nir_shader *nir,
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struct agx_shader_key *key,
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struct util_debug_callback *debug,
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struct util_dynarray *binary,
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struct agx_shader_info *out)
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agx_preprocess_nir(nir_shader *nir)
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{
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agx_debug = debug_get_option_agx_debug();
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memset(out, 0, sizeof *out);
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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out->writes_psiz = nir->info.outputs_written &
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BITFIELD_BIT(VARYING_SLOT_PSIZ);
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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out->no_colour_output = !(nir->info.outputs_written >> FRAG_RESULT_DATA0);
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}
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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/* Lower large arrays to scratch and small arrays to csel */
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@@ -1934,6 +1923,9 @@ agx_compile_shader_nir(nir_shader *nir,
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NIR_PASS_V(nir, nir_lower_io_to_scalar, nir_var_shader_out);
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}
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/* Clean up deref gunk after lowering I/O */
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NIR_PASS_V(nir, nir_opt_dce);
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nir_lower_tex_options lower_tex_options = {
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.lower_txp = ~0,
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.lower_invalid_implicit_lod = true,
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@@ -1954,6 +1946,31 @@ agx_compile_shader_nir(nir_shader *nir,
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NIR_PASS_V(nir, agx_lower_resinfo);
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NIR_PASS_V(nir, nir_legalize_16bit_sampler_srcs, tex_constraints);
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nir->info.io_lowered = true;
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}
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void
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agx_compile_shader_nir(nir_shader *nir,
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struct agx_shader_key *key,
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struct util_debug_callback *debug,
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struct util_dynarray *binary,
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struct agx_shader_info *out)
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{
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agx_debug = debug_get_option_agx_debug();
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memset(out, 0, sizeof *out);
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assert(nir->info.io_lowered &&
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"agx_preprocess_nir is called first, then the shader is specalized,"
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"then the specialized shader is compiled");
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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out->writes_psiz = nir->info.outputs_written &
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BITFIELD_BIT(VARYING_SLOT_PSIZ);
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
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out->no_colour_output = !(nir->info.outputs_written >> FRAG_RESULT_DATA0);
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}
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agx_optimize_nir(nir, &out->push_count);
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/* Implement conditional discard with real control flow like Metal */
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@@ -276,6 +276,9 @@ struct agx_shader_key {
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};
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};
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void
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agx_preprocess_nir(nir_shader *nir);
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void
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agx_compile_shader_nir(nir_shader *nir,
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struct agx_shader_key *key,
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@@ -70,6 +70,7 @@ agx_build_reload_shader(struct agx_device *dev)
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.fs.ignore_tib_dependencies = true,
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};
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agx_preprocess_nir(s);
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agx_compile_shader_nir(s, &key, NULL, &binary, &info);
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assert(offset + binary.size < bo_size);
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@@ -1078,6 +1078,7 @@ agx_compile_variant(struct agx_device *dev,
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}
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}
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agx_preprocess_nir(nir);
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agx_compile_shader_nir(nir, &key->base, debug, &binary, &compiled->info);
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if (binary.size) {
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