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radv: refactor the DGC helpers to determine cmdbuf size

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30737>
This commit is contained in:
Samuel Pitoiset
2024-08-20 11:24:50 +02:00
committed by Marge Bot
parent ca447a7a7e
commit 1048da8dd0
3 changed files with 22 additions and 20 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+1 -1
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@@ -11466,7 +11466,7 @@ radv_dgc_execute_ib(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommand
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const bool has_task_shader = radv_dgc_with_task_shader(pGeneratedCommandsInfo);
const uint32_t cmdbuf_size = radv_get_indirect_cmdbuf_size(pGeneratedCommandsInfo);
const uint32_t cmdbuf_size = radv_get_indirect_gfx_cmdbuf_size(pGeneratedCommandsInfo);
const uint64_t ib_va =
radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
src/amd/vulkan/radv_device_generated_commands.c
+20 -18
View File
@@ -232,32 +232,39 @@ radv_dgc_use_preamble(const VkGeneratedCommandsInfoNV *cmd_info)
return cmd_info->sequencesCountBuffer != VK_NULL_HANDLE && cmd_info->sequencesCount >= 64;
}
uint32_t
radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
static uint32_t
radv_get_indirect_cmdbuf_sequence_size(const VkGeneratedCommandsInfoNV *cmd_info, enum amd_ip_type ip_type)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, cmd_info->indirectCommandsLayout);
VK_FROM_HANDLE(radv_pipeline, pipeline, cmd_info->pipeline);
const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
uint32_t gfx_cmd_size, ace_cmd_size, upload_size;
radv_get_sequence_size(layout, pipeline, &gfx_cmd_size, &ace_cmd_size, &upload_size);
const uint32_t cmd_size = ip_type == AMD_IP_GFX ? gfx_cmd_size : ace_cmd_size;
return radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, ip_type);
}
uint32_t
radv_get_indirect_gfx_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, cmd_info->indirectCommandsLayout);
const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
if (radv_dgc_use_preamble(cmd_info))
return radv_dgc_preamble_cmdbuf_size(device, AMD_IP_GFX);
uint32_t cmd_size, ace_cmd_size, upload_size;
radv_get_sequence_size(layout, pipeline, &cmd_size, &ace_cmd_size, &upload_size);
return radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, AMD_IP_GFX);
return radv_get_indirect_cmdbuf_sequence_size(cmd_info, AMD_IP_GFX);
}
uint32_t
radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, cmd_info->indirectCommandsLayout);
VK_FROM_HANDLE(radv_pipeline, pipeline, cmd_info->pipeline);
const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
uint32_t cmd_size, ace_cmd_size, upload_size;
radv_get_sequence_size(layout, pipeline, &cmd_size, &ace_cmd_size, &upload_size);
uint32_t offset = radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, AMD_IP_GFX);
uint32_t offset = radv_get_indirect_cmdbuf_sequence_size(cmd_info, AMD_IP_GFX);
if (radv_dgc_use_preamble(cmd_info))
offset += radv_dgc_preamble_cmdbuf_size(device, AMD_IP_GFX);
@@ -269,15 +276,12 @@ uint32_t
radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
{
VK_FROM_HANDLE(radv_indirect_command_layout, layout, cmd_info->indirectCommandsLayout);
VK_FROM_HANDLE(radv_pipeline, pipeline, cmd_info->pipeline);
const struct radv_device *device = container_of(layout->base.device, struct radv_device, vk);
if (radv_dgc_use_preamble(cmd_info))
return radv_dgc_preamble_cmdbuf_size(device, AMD_IP_COMPUTE);
uint32_t cmd_size, ace_cmd_size, upload_size;
radv_get_sequence_size(layout, pipeline, &cmd_size, &ace_cmd_size, &upload_size);
return radv_align_cmdbuf_size(device, ace_cmd_size * cmd_info->sequencesCount, AMD_IP_COMPUTE);
return radv_get_indirect_cmdbuf_sequence_size(cmd_info, AMD_IP_COMPUTE);
}
struct radv_dgc_params {
@@ -2550,10 +2554,8 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
uint32_t cmd_stride, ace_cmd_stride, upload_stride;
radv_get_sequence_size(layout, pipeline, &cmd_stride, &ace_cmd_stride, &upload_stride);
unsigned cmd_buf_size =
radv_align_cmdbuf_size(device, cmd_stride * pGeneratedCommandsInfo->sequencesCount, AMD_IP_GFX);
unsigned ace_cmd_buf_size =
radv_align_cmdbuf_size(device, ace_cmd_stride * pGeneratedCommandsInfo->sequencesCount, AMD_IP_COMPUTE);
unsigned cmd_buf_size = radv_get_indirect_cmdbuf_sequence_size(pGeneratedCommandsInfo, AMD_IP_GFX);
unsigned ace_cmd_buf_size = radv_get_indirect_cmdbuf_sequence_size(pGeneratedCommandsInfo, AMD_IP_COMPUTE);
uint64_t upload_addr =
radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
src/amd/vulkan/radv_device_generated_commands.h
+1 -1
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@@ -54,7 +54,7 @@ struct radv_indirect_command_layout {
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_indirect_command_layout, base, VkIndirectCommandsLayoutNV,
VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NV)
uint32_t radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_gfx_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);