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ac: Improve description of some HW workarounds

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Also add references to their conterparts in old PAL code.
This makes it easier to remember whether we mitigated the
same issues as PAL did.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
This commit is contained in:
Timur Kristóf
2025-11-07 11:10:23 +01:00
parent cad4e7d2e7
commit 0d20bdbe2c
3 changed files with 5 additions and 5 deletions
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5
src/amd/common/ac_cmdbuf_cp.c
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@@ -447,7 +447,10 @@ ac_emit_cp_release_mem(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
{
const bool is_mec = gfx_level >= GFX7 && ip_type == AMD_IP_COMPUTE;
/* EOS events may be buggy on GFX7, prefer not to use them. */
/* GFX7 CP DMA: any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets are used.
* Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and DST_SEL=MC.
* Maybe related to waCpDmaHangMcTcAckDrop in PAL.
*/
if (gfx_level == GFX7 && (event == V_028A90_CS_DONE || event == V_028A90_PS_DONE))
event = V_028A90_BOTTOM_OF_PIPE_TS;

1
src/amd/common/ac_gpu_info.c
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@@ -958,6 +958,7 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
/* GFX6 hw bug when the IBO addr is 0 which causes invalid clamping (underflow).
* Setting the IB addr to 2 or higher solves this issue.
* See waMiscNullIb in PAL.
*/
info->has_null_index_buffer_clamping_bug = info->gfx_level == GFX6;

4
src/amd/common/sid.h
View File

@@ -202,10 +202,6 @@
#define EOS_DATA_SEL_APPEND_COUNT 0
#define EOS_DATA_SEL_GDS 1
#define EOS_DATA_SEL_VALUE_32BIT 2
/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
* DST_SEL=MC. Only GFX7 chips are affected.
*/
#define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8, breaks CP DMA */
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */
/* 1. header