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radv: add support for more HTILE clear codes

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The HTILE clear code is now computed based on the floating point value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>
This commit is contained in:
Samuel Pitoiset
2021-04-05 14:18:27 +02:00
parent 764960e16d
commit 0cfeb93751
1 changed files with 40 additions and 7 deletions
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src/amd/vulkan/radv_meta_clear.c
+40 -7
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@@ -868,19 +868,52 @@ static uint32_t
radv_get_htile_fast_clear_value(const struct radv_device *device, const struct radv_image *image,
VkClearDepthStencilValue value)
{
uint32_t clear_value;
uint32_t max_zval = 0x3fff; /* maximum 14-bit value. */
uint32_t zmask = 0, smem = 0;
uint32_t htile_value;
uint32_t zmin, zmax;
/* Convert the depth value to 14-bit zmin/zmax values. */
zmin = ((value.depth * max_zval) + 0.5f);
zmax = zmin;
if (radv_image_tile_stencil_disabled(device, image)) {
clear_value = value.depth ? 0xfffffff0 : 0;
/* Z only (no stencil):
*
* |31 18|17 4|3 0|
* +---------+---------+-------+
* | Max Z | Min Z | ZMask |
*/
htile_value = (((zmax & 0x3fff) << 18) |
((zmin & 0x3fff) << 4) |
((zmask & 0xf) << 0));
} else {
/* Z and stencil:
*
* |31 12|11 10|9 8|7 6|5 4|3 0|
* +-----------+-----+------+-----+-----+-------+
* | Z Range | | SMem | SR1 | SR0 | ZMask |
*
* Z, stencil, 4 bit VRS encoding:
* |31 12| 11 10 |9 8|7 6 |5 4|3 0|
* +-----------+------------+------+------------+-----+-------+
* | Z Range | VRS Y-rate | SMem | VRS X-rate | SR0 | ZMask |
*/
uint32_t delta = 0;
uint32_t zrange = ((zmax << 6) | delta);
uint32_t sresults = 0xf; /* SR0/SR1 both as 0x3. */
if (radv_image_has_vrs_htile(device, image))
clear_value = value.depth ? 0xfffc0030 : 0x30;
else {
clear_value = value.depth ? 0xfffc00f0 : 0xf0;
}
sresults = 0x3;
htile_value = (((zrange & 0xfffff) << 12) |
((smem & 0x3) << 8) |
((sresults & 0xf) << 4) |
((zmask & 0xf) << 0));
}
return clear_value;
return htile_value;
}
static uint32_t