broadcom/compiler: refactor image load/store TMU emission code
This mostly moves code around to group together the code involved with actually emitting a TMU sequence. This will make it a bit easier to then implement pipelining while reusing this code, similar to how we handled other cases of TMU pipelining. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8825>
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@@ -443,15 +443,56 @@ v3d40_vir_emit_image_load_store(struct v3d_compile *c,
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struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = { 0 };
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/* Limit the number of channels returned to both how many the NIR
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* instruction writes and how many the instruction could produce.
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*/
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uint32_t instr_return_channels = nir_intrinsic_dest_components(instr);
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if (!p1_unpacked.output_type_32_bit)
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instr_return_channels = (instr_return_channels + 1) / 2;
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p0_unpacked.return_words_of_texture_data =
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(1 << instr_return_channels) - 1;
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p2_unpacked.op = v3d40_image_load_store_tmu_op(instr);
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/* If we were able to replace atomic_add for an inc/dec, then we
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* need/can to do things slightly different, like not loading the
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* amount to add/sub, as that is implicit.
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*/
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bool atomic_add_replaced = (instr->intrinsic == nir_intrinsic_image_atomic_add &&
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(p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
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p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC));
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bool atomic_add_replaced =
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(instr->intrinsic == nir_intrinsic_image_atomic_add &&
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(p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
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p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC));
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uint32_t p0_packed;
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V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
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(uint8_t *)&p0_packed,
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&p0_unpacked);
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/* Load unit number into the high bits of the texture or sampler
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* address field, which will be be used by the driver to decide which
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* texture to put in the actual address field.
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*/
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p0_packed |= unit << 24;
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uint32_t p1_packed;
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V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
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(uint8_t *)&p1_packed,
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&p1_unpacked);
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uint32_t p2_packed;
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V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
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(uint8_t *)&p2_packed,
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&p2_unpacked);
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if (instr->intrinsic != nir_intrinsic_image_load)
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c->tmu_dirty_rcl = true;
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vir_WRTMUC(c, QUNIFORM_IMAGE_TMU_CONFIG_P0, p0_packed);
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if (memcmp(&p1_unpacked, &p1_unpacked_default, sizeof(p1_unpacked)) != 0)
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vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed);
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if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
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vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
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bool is_1d = false;
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switch (nir_intrinsic_image_dim(instr)) {
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@@ -486,43 +527,6 @@ v3d40_vir_emit_image_load_store(struct v3d_compile *c,
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is_1d ? 1 : 2), &tmu_writes);
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}
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/* Limit the number of channels returned to both how many the NIR
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* instruction writes and how many the instruction could produce.
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*/
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uint32_t instr_return_channels = nir_intrinsic_dest_components(instr);
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if (!p1_unpacked.output_type_32_bit)
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instr_return_channels = (instr_return_channels + 1) / 2;
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p0_unpacked.return_words_of_texture_data =
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(1 << instr_return_channels) - 1;
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uint32_t p0_packed;
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V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
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(uint8_t *)&p0_packed,
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&p0_unpacked);
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uint32_t p1_packed;
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V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
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(uint8_t *)&p1_packed,
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&p1_unpacked);
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uint32_t p2_packed;
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V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
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(uint8_t *)&p2_packed,
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&p2_unpacked);
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/* Load unit number into the high bits of the texture or sampler
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* address field, which will be be used by the driver to decide which
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* texture to put in the actual address field.
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*/
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p0_packed |= unit << 24;
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vir_WRTMUC(c, QUNIFORM_IMAGE_TMU_CONFIG_P0, p0_packed);
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if (memcmp(&p1_unpacked, &p1_unpacked_default, sizeof(p1_unpacked)) != 0)
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vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed);
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if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
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vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
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/* Emit the data writes for atomics or image store. */
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if (instr->intrinsic != nir_intrinsic_image_load &&
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!atomic_add_replaced) {
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@@ -573,7 +577,4 @@ v3d40_vir_emit_image_load_store(struct v3d_compile *c,
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if (nir_intrinsic_dest_components(instr) == 0)
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vir_TMUWT(c);
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if (instr->intrinsic != nir_intrinsic_image_load)
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c->tmu_dirty_rcl = true;
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}
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