intel/executor: Add example using scalar register and send gather
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32236>
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@@ -0,0 +1,71 @@
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-- Xe3 adds a new ARF to store scalar values. It supports only a limited
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-- set of operations.
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check_ver(30)
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local r = execute {
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src=[[
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// The new scalar register s0 has 32 bytes.
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//
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// Only MOV can have scalar as destination. Offsets in scalar
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// must be aligned to word boundary. This non-overlapping MOVs
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// will fill the first 16 bytes.
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mov(1) s0<1>UW 0x1111UW;
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mov(1) r2<1>UW 0x2222UW;
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mov(1) s0.1<1>UW r2<0,1,0>UW {I@1};
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mov(1) s0.1<1>UD 0x33333333UD {I@1};
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mov(4) r4<1>UW 0x4444UW;
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mov(1) s0.1<1>UQ r4<0,1,0>UQ {I@1};
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// Scalar content can be broadcasted back into GRFs.
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mov(16) r20<1>UD s0.0<0,1,0>UD;
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mov(16) r32<1>UD s0.1<0,1,0>UD;
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mov(16) r96<1>UD s0.2<0,1,0>UD;
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mov(16) r64<1>UD s0.3<0,1,0>UD;
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// Scalar can store a list of register numbers to be used as source for
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// SEND. Note the scalar will contain the hex value for r11 and r20.
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// And the scalar register is indexed as bytes in r[...] syntax, unlike
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// in the MOV.
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mov(16) r11<1>UD 0x30000000UD;
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mov(1) s0.4<1>UD 0x0000140bUD;
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send(16) nullUD r[s0.16] 0x04000504 0x00000000 ugm MsgDesc: () { I@1 $1 };
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// A larger SEND, note that registers for the payload don't need to be
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// contiguous, the hardware will gather them together.
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add(16) r11<1>UD r11<1,1,0>UD 0x4UD {A@1, $1.src};
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mov(1) s0.4<1>UD 0x4060200bUD;
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send(16) nullUD r[s0.16] 0x08002504 0x00000000 ugm MsgDesc: ( ) { I@1 $1 };
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@eot
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]]
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}
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expected = {[0] = 0x22221111, 0x33333333, 0x44444444, 0x44444444}
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print("result")
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dump(r, 4)
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print("expected")
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dump(expected, 4)
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for i=0,3 do
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if r[i] ~= expected[i] then
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print("FAIL")
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return
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end
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end
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print("OK")
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