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intel/isl: Use an allow-list in gfx6_filter_tiling

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Try to avoid having to update isl_gfx6_filter_tiling when new tilings
are added for new platforms. Note that the allow-list uses
ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
added in the future.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
This commit is contained in:
Nanley Chery
2021-07-29 17:04:14 -07:00
committed by Marge Bot
parent 602f597bc1
commit 0ab2fa18e4
1 changed files with 15 additions and 3 deletions
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src/intel/isl/isl_gfx7.c
+15 -3
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@@ -197,9 +197,21 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
/* Clear flags unsupported on this hardware */
if (ISL_GFX_VER(dev) < 9) {
*flags &= ~ISL_TILING_Yf_BIT;
*flags &= ~ISL_TILING_Ys_BIT;
assert(ISL_GFX_VERX10(dev) < 125);
if (ISL_GFX_VER(dev) >= 12) {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_ANY_Y_MASK;
} else if (ISL_GFX_VER(dev) >= 9) {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_W_BIT |
ISL_TILING_ANY_Y_MASK;
} else {
*flags &= ISL_TILING_LINEAR_BIT |
ISL_TILING_X_BIT |
ISL_TILING_W_BIT |
ISL_TILING_Y0_BIT;
}
/* And... clear the Yf and Ys bits anyway because Anvil doesn't support