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/**************************************************************************
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Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
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VA Linux Systems Inc., Fremont, California.
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The Weather Channel (TM) funded Tungsten Graphics to develop the
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initial release of the Radeon 8500 driver under the XFree86 license.
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This notice must be preserved.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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*/
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#include "glheader.h"
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#include "swrast/swrast.h"
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#include "r300_state.h"
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#include "radeon_ioctl.h"
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#include "r300_ioctl.h"
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#include "radeon_span.h"
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#include "drirenderbuffer.h"
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#define DBG 0
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/*
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* Note that all information needed to access pixels in a renderbuffer
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* should be obtained through the gl_renderbuffer parameter, not per-context
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* information.
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*/
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#define LOCAL_VARS \
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driRenderbuffer *drb = (driRenderbuffer *) rb; \
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const __DRIdrawablePrivate *dPriv = drb->dPriv; \
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const GLuint bottom = dPriv->h - 1; \
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GLubyte *buf = (GLubyte *) drb->flippedData \
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+ (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp; \
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GLuint p; \
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(void) p;
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#define LOCAL_DEPTH_VARS \
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driRenderbuffer *drb = (driRenderbuffer *) rb; \
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const __DRIdrawablePrivate *dPriv = drb->dPriv; \
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const GLuint bottom = dPriv->h - 1; \
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GLuint xo = dPriv->x; \
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GLuint yo = dPriv->y; \
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GLubyte *buf = (GLubyte *) drb->Base.Data;
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#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
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#define Y_FLIP(Y) (bottom - (Y))
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#define HW_LOCK()
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#define HW_UNLOCK()
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/* ================================================================
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* Color buffer
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*/
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/* 16 bit, RGB565 color spanline and pixel functions
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*/
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#define SPANTMP_PIXEL_FMT GL_RGB
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
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#define TAG(x) radeon##x##_RGB565
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#define TAG2(x,y) radeon##x##_RGB565##y
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#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
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#include "spantmp2.h"
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/* 32 bit, ARGB8888 color spanline and pixel functions
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*/
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#define SPANTMP_PIXEL_FMT GL_BGRA
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#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
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#define TAG(x) radeon##x##_ARGB8888
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#define TAG2(x,y) radeon##x##_ARGB8888##y
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#define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
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#include "spantmp2.h"
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/* ================================================================
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* Depth buffer
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*/
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/* The Radeon family has depth tiling on all the time, so we have to convert
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* the x,y coordinates into the memory bus address (mba) in the same
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* manner as the engine. In each case, the linear block address (ba)
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* is calculated, and then wired with x and y to produce the final
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* memory address.
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* The chip will do address translation on its own if the surface registers
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* are set up correctly. It is not quite enough to get it working with hyperz
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* too...
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*/
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static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
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{
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GLuint pitch = drb->pitch;
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if (drb->depthHasSurface) {
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return 4 * (x + y * pitch);
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} else {
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GLuint ba, address = 0; /* a[0..1] = 0 */
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#ifdef COMPILE_R300
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ba = (y / 8) * (pitch / 8) + (x / 8);
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#else
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ba = (y / 16) * (pitch / 16) + (x / 16);
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#endif
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address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
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address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
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address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
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address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
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address |= (y & 0x8) << 7; /* a[10] = y[3] */
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address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
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address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
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return address;
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}
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}
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static INLINE GLuint
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radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
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{
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GLuint pitch = drb->pitch;
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if (drb->depthHasSurface) {
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return 2 * (x + y * pitch);
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} else {
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GLuint ba, address = 0; /* a[0] = 0 */
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ba = (y / 16) * (pitch / 32) + (x / 32);
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address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
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address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
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address |= (x & 0x8) << 4; /* a[7] = x[3] */
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address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
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address |= (y & 0x8) << 7; /* a[10] = y[3] */
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address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
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address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
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return address;
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}
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}
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/* 16-bit depth buffer functions
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*/
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#define WRITE_DEPTH( _x, _y, d ) \
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*(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
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#define READ_DEPTH( d, _x, _y ) \
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d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
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#define TAG(x) radeon##x##_z16
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#include "depthtmp.h"
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/* 24 bit depth, 8 bit stencil depthbuffer functions
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*
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* Careful: It looks like the R300 uses ZZZS byte order while the R200
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* uses SZZZ for 24 bit depth, 8 bit stencil mode.
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*/
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#ifdef COMPILE_R300
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#define WRITE_DEPTH( _x, _y, d ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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tmp &= 0x000000ff; \
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tmp |= ((d << 8) & 0xffffff00); \
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*(GLuint *)(buf + offset) = tmp; \
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} while (0)
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#else
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#define WRITE_DEPTH( _x, _y, d ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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tmp &= 0xff000000; \
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tmp |= ((d) & 0x00ffffff); \
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*(GLuint *)(buf + offset) = tmp; \
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} while (0)
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#endif
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#ifdef COMPILE_R300
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#define READ_DEPTH( d, _x, _y ) \
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do { \
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d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
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_y + yo )) & 0xffffff00) >> 8; \
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}while(0)
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#else
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#define READ_DEPTH( d, _x, _y ) \
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d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo, \
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_y + yo )) & 0x00ffffff;
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#endif
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#define TAG(x) radeon##x##_z24_s8
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#include "depthtmp.h"
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/* ================================================================
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* Stencil buffer
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*/
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/* 24 bit depth, 8 bit stencil depthbuffer functions
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*/
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#ifdef COMPILE_R300
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#define WRITE_STENCIL( _x, _y, d ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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tmp &= 0xffffff00; \
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tmp |= (d) & 0xff; \
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*(GLuint *)(buf + offset) = tmp; \
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} while (0)
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#else
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#define WRITE_STENCIL( _x, _y, d ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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tmp &= 0x00ffffff; \
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tmp |= (((d) & 0xff) << 24); \
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*(GLuint *)(buf + offset) = tmp; \
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} while (0)
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#endif
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#ifdef COMPILE_R300
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#define READ_STENCIL( d, _x, _y ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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d = tmp & 0x000000ff; \
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} while (0)
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#else
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#define READ_STENCIL( d, _x, _y ) \
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do { \
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GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo ); \
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GLuint tmp = *(GLuint *)(buf + offset); \
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d = (tmp & 0xff000000) >> 24; \
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} while (0)
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#endif
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#define TAG(x) radeon##x##_z24_s8
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#include "stenciltmp.h"
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/* Move locking out to get reasonable span performance (10x better
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* than doing this in HW_LOCK above). WaitForIdle() is the main
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* culprit.
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*/
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static void radeonSpanRenderStart(GLcontext * ctx)
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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#ifdef COMPILE_R300
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r300ContextPtr r300 = (r300ContextPtr) rmesa;
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R300_FIREVERTICES(r300);
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#else
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RADEON_FIREVERTICES(rmesa);
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#endif
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LOCK_HARDWARE(rmesa);
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radeonWaitForIdleLocked(rmesa);
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}
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static void radeonSpanRenderFinish(GLcontext * ctx)
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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_swrast_flush(ctx);
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UNLOCK_HARDWARE(rmesa);
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}
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void radeonInitSpanFuncs(GLcontext * ctx)
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{
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struct swrast_device_driver *swdd =
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_swrast_GetDeviceDriverReference(ctx);
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swdd->SpanRenderStart = radeonSpanRenderStart;
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swdd->SpanRenderFinish = radeonSpanRenderFinish;
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}
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/**
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* Plug in the Get/Put routines for the given driRenderbuffer.
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*/
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void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
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{
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if (drb->Base.InternalFormat == GL_RGBA) {
|
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|
|
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if (vis->redBits == 5 && vis->greenBits == 6
|
|
|
|
|
&& vis->blueBits == 5) {
|
|
|
|
|
radeonInitPointers_RGB565(&drb->Base);
|
|
|
|
|
} else {
|
|
|
|
|
radeonInitPointers_ARGB8888(&drb->Base);
|
|
|
|
|
}
|
|
|
|
|
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
|
|
|
|
|
radeonInitDepthPointers_z16(&drb->Base);
|
|
|
|
|
} else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
|
|
|
|
|
radeonInitDepthPointers_z24_s8(&drb->Base);
|
|
|
|
|
} else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
|
|
|
|
|
radeonInitStencilPointers_z24_s8(&drb->Base);
|
|
|
|
|
}
|
|
|
|
|
}
|
Oliver McFadden