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radv: Move NIR specific function declarations to radv_meta_nir.h

Browse Source 
Also rename some functions for consistency with other functions,
and slightly change the includes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33494>
This commit is contained in:
Timur Kristóf
2025-02-11 14:20:27 +01:00
committed by Marge Bot
parent f6a02d034b
commit 09db738c9a
23 changed files with 194 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/meson.build
+1
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@@ -63,6 +63,7 @@ libradv_files = files(
'meta/radv_meta_resolve_cs.c',
'meta/radv_meta_resolve_fs.c',
'nir/radv_meta_nir.c',
'nir/radv_meta_nir.h',
'nir/radv_nir.h',
'nir/radv_nir_apply_pipeline_layout.c',
'nir/radv_nir_export_multiview.c',
src/amd/vulkan/meta/radv_meta.h
-87
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@@ -257,93 +257,6 @@ void radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image
void radv_meta_decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkImageLayout layout,
const VkImageSubresourceLayers *subresource, VkOffset3D offset, VkExtent3D extent);
/* common nir builder helpers */
#include "nir/nir_builder.h"
nir_builder PRINTFLIKE(3, 4)
radv_meta_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...);
nir_shader *radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev);
nir_shader *radv_meta_build_nir_fs_noop(struct radv_device *dev);
void radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer, int samples,
nir_variable *input_img, nir_variable *color, nir_def *img_coord);
nir_def *radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding);
nir_def *get_global_ids(nir_builder *b, unsigned num_components);
void radv_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
nir_shader *radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_buffer_copy_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev,
enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d);
nir_shader *radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d);
nir_shader *radv_meta_nir_build_btoi_r32g32b32_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bool dst_3d, int samples);
nir_shader *radv_meta_nir_build_itoi_r32g32b32_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples);
nir_shader *radv_meta_nir_build_cleari_r32g32b32_compute_shader(struct radv_device *dev);
typedef nir_def *(*radv_meta_nir_texel_fetch_build_func)(struct nir_builder *, struct radv_device *, nir_def *, bool,
bool);
nir_def *radv_meta_nir_build_blit2d_texel_fetch(struct nir_builder *b, struct radv_device *device, nir_def *tex_pos,
bool is_3d, bool is_multisampled);
nir_def *radv_meta_nir_build_blit2d_buffer_fetch(struct nir_builder *b, struct radv_device *device, nir_def *tex_pos,
bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
void radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, uint32_t frag_output);
void radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, bool unrestricted);
nir_shader *radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa);
nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf);
nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf);
nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int samples);
nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int samples);
enum radv_meta_resolve_type {
RADV_META_DEPTH_RESOLVE,
RADV_META_STENCIL_RESOLVE,
};
nir_shader *radv_meta_nir_build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb,
int samples);
nir_shader *radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
enum radv_meta_resolve_type index,
VkResolveModeFlagBits resolve_mode);
nir_shader *radv_meta_nir_build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples);
nir_shader *radv_meta_nir_build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
enum radv_meta_resolve_type index,
VkResolveModeFlagBits resolve_mode);
nir_shader *radv_meta_nir_build_resolve_fs(struct radv_device *dev);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value);
src/amd/vulkan/meta/radv_meta_blit.c
+1
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_meta.h"
#include "vk_command_pool.h"
#include "vk_common_entrypoints.h"
src/amd/vulkan/meta/radv_meta_blit2d.c
+1
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@@ -7,6 +7,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_meta.h"
#include "vk_common_entrypoints.h"
src/amd/vulkan/meta/radv_meta_buffer.c
+1
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@@ -1,6 +1,7 @@
#include "radv_cp_dma.h"
#include "radv_debug.h"
#include "radv_meta.h"
#include "nir/radv_meta_nir.h"
#include "radv_sdma.h"
#include "radv_cs.h"
src/amd/vulkan/meta/radv_meta_bufimage.c
+1
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@@ -5,6 +5,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_meta.h"
#include "vk_common_entrypoints.h"
src/amd/vulkan/meta/radv_meta_clear.c
+1
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_debug.h"
#include "radv_entrypoints.h"
#include "radv_formats.h"
src/amd/vulkan/meta/radv_meta_copy.c
+1
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_formats.h"
#include "radv_meta.h"
#include "radv_sdma.h"
src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
+1
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "ac_surface.h"
#include "radv_meta.h"
#include "vk_common_entrypoints.h"
src/amd/vulkan/meta/radv_meta_dcc_retile.c
+1
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@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "ac_surface.h"
#include "radv_meta.h"
#include "vk_common_entrypoints.h"
src/amd/vulkan/meta/radv_meta_decompress.c
+3 -2
View File
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include "nir/radv_meta_nir.h"
#include "radv_meta.h"
#include "sid.h"
@@ -36,8 +37,8 @@ get_pipeline_gfx(struct radv_device *device, struct radv_image *image, VkPipelin
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_nir_build_fs_noop(device);
const VkPipelineSampleLocationsStateCreateInfoEXT sample_locs_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT,
src/amd/vulkan/meta/radv_meta_fast_clear.c
+3 -2
View File
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include "nir/radv_meta_nir.h"
#include "radv_meta.h"
enum radv_color_op {
@@ -107,8 +108,8 @@ get_pipeline(struct radv_device *device, enum radv_color_op op, VkPipeline *pipe
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_build_nir_fs_noop(device);
nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_nir_build_fs_noop(device);
VkGraphicsPipelineCreateInfoRADV radv_info = {
.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV,
src/amd/vulkan/meta/radv_meta_fmask_copy.c
+1
View File
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_formats.h"
#include "radv_meta.h"
src/amd/vulkan/meta/radv_meta_fmask_expand.c
+1
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@@ -5,6 +5,7 @@
* SPDX-License-Identifier: MIT
*/
#include "nir/radv_meta_nir.h"
#include "radv_formats.h"
#include "radv_meta.h"
#include "vk_format.h"
src/amd/vulkan/meta/radv_meta_resolve.c
+2 -1
View File
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_meta.h"
#include "vk_format.h"
@@ -37,7 +38,7 @@ get_pipeline(struct radv_device *device, unsigned fs_key, VkPipeline *pipeline_o
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_nir_build_resolve_fs(device);
const VkGraphicsPipelineCreateInfoRADV radv_info = {
src/amd/vulkan/meta/radv_meta_resolve_cs.c
+1
View File
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_formats.h"
#include "radv_meta.h"
src/amd/vulkan/meta/radv_meta_resolve_fs.c
+3 -2
View File
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_meta.h"
#include "vk_common_entrypoints.h"
@@ -73,7 +74,7 @@ get_depth_stencil_resolve_pipeline(struct radv_device *device, int samples, VkIm
nir_shader *fs_module =
radv_meta_nir_build_depth_stencil_resolve_fragment_shader(device, samples, index, resolve_mode);
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
const VkStencilOp stencil_op = index == RADV_META_DEPTH_RESOLVE ? VK_STENCIL_OP_KEEP : VK_STENCIL_OP_REPLACE;
@@ -225,7 +226,7 @@ get_color_resolve_pipeline(struct radv_device *device, struct radv_image_view *s
return VK_SUCCESS;
}
nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device);
nir_shader *vs_module = radv_meta_nir_build_vs_generate_vertices(device);
nir_shader *fs_module = radv_meta_nir_build_resolve_fragment_shader(device, is_integer, samples);
const VkGraphicsPipelineCreateInfo pipeline_create_info = {
src/amd/vulkan/nir/radv_meta_nir.c
+49 -47
View File
@@ -10,12 +10,14 @@
#define AC_SURFACE_INCLUDE_NIR
#include "ac_surface.h"
#include "../meta/radv_meta.h"
#include "nir/nir_format_convert.h"
#include "nir_builder.h"
#include "radv_meta_nir.h"
#include "radv_device.h"
#include "radv_physical_device.h"
nir_builder PRINTFLIKE(3, 4)
radv_meta_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...)
radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...)
{
const struct radv_physical_device *pdev = radv_device_physical(dev);
nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);
@@ -35,13 +37,13 @@ nir_builder PRINTFLIKE(3, 4)
/* vertex shader that generates vertices */
nir_shader *
radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev)
radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_variable *v_position;
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_vs_gen_verts");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_vs_gen_verts");
nir_def *outvec = nir_gen_rect_vertices(&b, NULL, NULL);
@@ -54,13 +56,13 @@ radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev)
}
nir_shader *
radv_meta_build_nir_fs_noop(struct radv_device *dev)
radv_meta_nir_build_fs_noop(struct radv_device *dev)
{
return radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
return radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
}
void
radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer, int samples,
static void
radv_meta_nir_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer, int samples,
nir_variable *input_img, nir_variable *color, nir_def *img_coord)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
@@ -94,7 +96,7 @@ radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b,
}
nir_def *
radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
radv_meta_nir_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
{
nir_def *rsrc = nir_vulkan_resource_index(b, 3, 32, nir_imm_int(b, 0), .desc_set = desc_set, .binding = binding);
return nir_trim_vector(b, rsrc, 2);
@@ -117,7 +119,7 @@ get_global_ids(nir_builder *b, unsigned num_components)
}
void
radv_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
{
nir_def *counter = nir_load_var(b, var);
@@ -130,7 +132,7 @@ radv_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
nir_shader *
radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_fill");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_fill");
b.shader->info.workgroup_size[0] = 64;
nir_def *pconst = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 16);
@@ -152,7 +154,7 @@ radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev)
nir_shader *
radv_meta_nir_build_buffer_copy_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_copy");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_copy");
b.shader->info.workgroup_size[0] = 64;
nir_def *pconst = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range = 16);
@@ -176,7 +178,7 @@ nir_shader *
radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_blit_vs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_blit_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -218,7 +220,7 @@ nir_shader *
radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -250,7 +252,7 @@ nir_shader *
radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_depth_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -282,7 +284,7 @@ nir_shader *
radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev, enum glsl_sampler_dim tex_dim)
{
const struct glsl_type *vec4 = glsl_vec4_type();
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_blit_stencil_fs.%d", tex_dim);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec4, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -315,7 +317,7 @@ radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_VERTEX, "meta_blit2d_vs");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_VERTEX, "meta_blit2d_vs");
nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
pos_out->data.location = VARYING_SLOT_POS;
@@ -411,7 +413,7 @@ radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -437,7 +439,7 @@ radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -463,7 +465,7 @@ radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *devi
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_FRAGMENT, "%s", name);
nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "v_tex_pos");
tex_pos_in->data.location = VARYING_SLOT_VAR0;
@@ -488,7 +490,7 @@ radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d)
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *sampler_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
@@ -528,7 +530,7 @@ radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d)
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
@@ -568,7 +570,7 @@ radv_meta_nir_build_btoi_r32g32b32_compute_shader(struct radv_device *dev)
{
const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_btoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, buf_type, "s_tex");
@@ -622,7 +624,7 @@ radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bo
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *buf_type = glsl_sampler_type(src_dim, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(dst_dim, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_cs-%dd-%dd-%d", src_3d ? 3 : 2,
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_cs-%dd-%dd-%d", src_3d ? 3 : 2,
dst_3d ? 3 : 2, samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -669,7 +671,7 @@ radv_meta_nir_build_itoi_r32g32b32_compute_shader(struct radv_device *dev)
{
const struct glsl_type *type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_itoi_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "input_img");
@@ -723,7 +725,7 @@ radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, i
: GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, false, GLSL_TYPE_FLOAT);
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, is_3d ? "meta_cleari_cs_3d-%d" : "meta_cleari_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -756,7 +758,7 @@ nir_shader *
radv_meta_nir_build_cleari_r32g32b32_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_cleari_r32g32b32_cs");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -790,8 +792,8 @@ void
radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs, struct nir_shader **out_fs,
uint32_t frag_output)
{
nir_builder vs_b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_clear_color_vs");
nir_builder fs_b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
nir_builder vs_b = radv_meta_nir_init_shader(dev, MESA_SHADER_VERTEX, "meta_clear_color_vs");
nir_builder fs_b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_clear_color_fs-%d", frag_output);
const struct glsl_type *position_type = glsl_vec4_type();
const struct glsl_type *color_type = glsl_vec4_type();
@@ -827,10 +829,10 @@ void
radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, bool unrestricted)
{
nir_builder vs_b = radv_meta_init_shader(
nir_builder vs_b = radv_meta_nir_init_shader(
dev, MESA_SHADER_VERTEX, unrestricted ? "meta_clear_depthstencil_unrestricted_vs" : "meta_clear_depthstencil_vs");
nir_builder fs_b =
radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT,
radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT,
unrestricted ? "meta_clear_depthstencil_unrestricted_fs" : "meta_clear_depthstencil_fs");
const struct glsl_type *position_out_type = glsl_vec4_type();
@@ -871,7 +873,7 @@ radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct n
nir_shader *
radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev)
{
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_htile_mask");
b.shader->info.workgroup_size[0] = 64;
nir_def *global_id = get_global_ids(&b, 1);
@@ -904,7 +906,7 @@ radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, boo
enum glsl_sampler_dim dim = is_msaa ? GLSL_SAMPLER_DIM_MS : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *img_type = glsl_image_type(dim, true, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_clear_dcc_comp_to_single-%s",
is_msaa ? "multisampled" : "singlesampled");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -942,7 +944,7 @@ nir_shader *
radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1026,7 +1028,7 @@ radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, struct ra
const struct radv_physical_device *pdev = radv_device_physical(dev);
enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF;
const struct glsl_type *buf_type = glsl_image_type(dim, false, GLSL_TYPE_UINT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_retile_compute");
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1074,7 +1076,7 @@ radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "expand_depth_stencil_compute");
/* We need at least 8/8/1 to cover an entire HTILE block in a single workgroup. */
b.shader->info.workgroup_size[0] = 8;
@@ -1114,7 +1116,7 @@ radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev)
{
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_decompress_compute");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "dcc_decompress_compute");
/* We need at least 16/16/1 to cover an entire DCC block in a single workgroup. */
b.shader->info.workgroup_size[0] = 16;
@@ -1152,7 +1154,7 @@ radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int sampl
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1214,7 +1216,7 @@ radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int sampl
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->def, dst_coord, sample_id, outval,
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_MS);
radv_break_on_count(&b, counter, max_sample_index);
radv_meta_nir_break_on_count(&b, counter, max_sample_index);
}
nir_pop_loop(&b, loop);
@@ -1227,7 +1229,7 @@ radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int
const struct glsl_type *type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, true, GLSL_TYPE_FLOAT);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1278,7 +1280,7 @@ radv_meta_nir_build_resolve_compute_shader(struct radv_device *dev, bool is_inte
enum glsl_base_type img_base_type = is_integer ? GLSL_TYPE_UINT : GLSL_TYPE_FLOAT;
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, img_base_type);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, img_base_type);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
is_integer ? "int" : (is_srgb ? "srgb" : "float"));
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = 8;
@@ -1301,7 +1303,7 @@ radv_meta_nir_build_resolve_compute_shader(struct radv_device *dev, bool is_inte
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
radv_meta_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, src_coord);
radv_meta_nir_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, src_coord);
nir_def *outval = nir_load_var(&b, color);
if (is_srgb)
@@ -1341,7 +1343,7 @@ radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, img_base_type);
const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, true, img_base_type);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
index == RADV_META_DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
b.shader->info.workgroup_size[0] = 8;
@@ -1412,7 +1414,7 @@ radv_meta_nir_build_resolve_fragment_shader(struct radv_device *dev, bool is_int
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, img_base_type);
nir_builder b =
radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
input_img->data.descriptor_set = 0;
@@ -1429,7 +1431,7 @@ radv_meta_nir_build_resolve_fragment_shader(struct radv_device *dev, bool is_int
nir_def *img_coord = nir_trim_vector(&b, nir_iadd(&b, pos_int, src_offset), 2);
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
radv_meta_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, img_coord);
radv_meta_nir_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, img_coord);
nir_def *outval = nir_load_var(&b, color);
nir_store_var(&b, color_out, outval, 0xf);
@@ -1445,7 +1447,7 @@ radv_meta_nir_build_depth_stencil_resolve_fragment_shader(struct radv_device *de
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, img_base_type);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
index == RADV_META_DEPTH_RESOLVE ? "depth" : "stencil",
get_resolve_mode_str(resolve_mode), samples);
@@ -1506,7 +1508,7 @@ radv_meta_nir_build_resolve_fs(struct radv_device *dev)
const struct glsl_type *vec4 = glsl_vec4_type();
nir_variable *f_color;
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs");
f_color = nir_variable_create(b.shader, nir_var_shader_out, vec4, "f_color");
f_color->data.location = FRAG_RESULT_DATA0;
src/amd/vulkan/nir/radv_meta_nir.h
+107
View File
@@ -0,0 +1,107 @@
/* Based on anv:
* Copyright © 2015 Intel Corporation
*
* Copyright © 2016 Red Hat Inc.
* Copyright © 2018 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#ifndef RADV_META_NIR_H
#define RADV_META_NIR_H
#include "vulkan/vulkan_core.h"
#include "nir_builder.h"
#ifdef __cplusplus
extern "C" {
#endif
struct radv_device;
struct radeon_surf;
nir_builder PRINTFLIKE(3, 4)
radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...);
nir_shader *radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev);
nir_shader *radv_meta_nir_build_fs_noop(struct radv_device *dev);
nir_def *get_global_ids(nir_builder *b, unsigned num_components);
void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
nir_shader *radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_buffer_copy_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev,
enum glsl_sampler_dim tex_dim);
nir_shader *radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d);
nir_shader *radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d);
nir_shader *radv_meta_nir_build_btoi_r32g32b32_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bool dst_3d, int samples);
nir_shader *radv_meta_nir_build_itoi_r32g32b32_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples);
nir_shader *radv_meta_nir_build_cleari_r32g32b32_compute_shader(struct radv_device *dev);
typedef nir_def *(*radv_meta_nir_texel_fetch_build_func)(struct nir_builder *, struct radv_device *, nir_def *, bool,
bool);
nir_def *radv_meta_nir_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding);
nir_def *radv_meta_nir_build_blit2d_texel_fetch(struct nir_builder *b, struct radv_device *device, nir_def *tex_pos,
bool is_3d, bool is_multisampled);
nir_def *radv_meta_nir_build_blit2d_buffer_fetch(struct nir_builder *b, struct radv_device *device, nir_def *tex_pos,
bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *device,
radv_meta_nir_texel_fetch_build_func txf_func,
const char *name, bool is_3d, bool is_multisampled);
void radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, uint32_t frag_output);
void radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
struct nir_shader **out_fs, bool unrestricted);
nir_shader *radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa);
nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf);
nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf);
nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int samples);
nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int samples);
enum radv_meta_resolve_type {
RADV_META_DEPTH_RESOLVE,
RADV_META_STENCIL_RESOLVE,
};
nir_shader *radv_meta_nir_build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb,
int samples);
nir_shader *radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
enum radv_meta_resolve_type index,
VkResolveModeFlagBits resolve_mode);
nir_shader *radv_meta_nir_build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples);
nir_shader *radv_meta_nir_build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
enum radv_meta_resolve_type index,
VkResolveModeFlagBits resolve_mode);
nir_shader *radv_meta_nir_build_resolve_fs(struct radv_device *dev);
#ifdef __cplusplus
}
#endif
#endif /* RADV_META_NIR_H */
src/amd/vulkan/nir/radv_nir_rt_shader.c
+2 -1
View File
@@ -9,6 +9,7 @@
#include "bvh/bvh.h"
#include "meta/radv_meta.h"
#include "nir/radv_meta_nir.h"
#include "nir/radv_nir.h"
#include "nir/radv_nir_rt_common.h"
#include "ac_nir.h"
@@ -1699,7 +1700,7 @@ radv_build_traversal_shader(struct radv_device *device, struct radv_ray_tracing_
/* Create the traversal shader as an intersection shader to prevent validation failures due to
* invalid variable modes.*/
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_INTERSECTION, "rt_traversal");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_INTERSECTION, "rt_traversal");
b.shader->info.internal = false;
b.shader->info.workgroup_size[0] = 8;
b.shader->info.workgroup_size[1] = pdev->rt_wave_size == 64 ? 8 : 4;
src/amd/vulkan/radv_dgc.c
+2 -1
View File
@@ -6,6 +6,7 @@
#include "radv_dgc.h"
#include "meta/radv_meta.h"
#include "nir/radv_meta_nir.h"
#include "radv_entrypoints.h"
#include "radv_pipeline_rt.h"
@@ -2470,7 +2471,7 @@ static nir_shader *
build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_layout *layout)
{
const struct radv_physical_device *pdev = radv_device_physical(dev);
nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_dgc_prepare");
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_dgc_prepare");
b.shader->info.workgroup_size[0] = 64;
nir_def *global_id = get_global_ids(&b, 1);
src/amd/vulkan/radv_query.c
+9 -8
View File
@@ -14,6 +14,7 @@
#include "bvh/bvh.h"
#include "meta/radv_meta.h"
#include "nir/nir_builder.h"
#include "nir/radv_meta_nir.h"
#include "util/u_atomic.h"
#include "vulkan/vulkan_core.h"
#include "radv_cs.h"
@@ -155,7 +156,7 @@ build_occlusion_query_shader(struct radv_device *device)
* }
*/
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "occlusion_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "occlusion_query");
b.shader->info.workgroup_size[0] = 64;
nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
@@ -213,7 +214,7 @@ build_occlusion_query_shader(struct radv_device *device)
nir_push_loop(&b);
nir_def *current_outer_count = nir_load_var(&b, outer_counter);
radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
radv_meta_nir_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
nir_def *enabled_cond = nir_iand_imm(&b, nir_ishl(&b, nir_imm_int64(&b, 1), current_outer_count), enabled_rb_mask);
@@ -447,7 +448,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
* }
*/
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "pipeline_statistics_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "pipeline_statistics_query");
b.shader->info.workgroup_size[0] = 64;
nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
@@ -567,7 +568,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
nir_loop *loop = nir_push_loop(&b);
nir_def *current_counter = nir_load_var(&b, counter);
radv_break_on_count(&b, counter, elem_count);
radv_meta_nir_break_on_count(&b, counter, elem_count);
nir_def *output_elem = nir_iadd(&b, output_base, nir_imul(&b, elem_size, current_counter));
nir_push_if(&b, result_is_64bit);
@@ -841,7 +842,7 @@ build_tfb_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "tfb_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "tfb_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */
@@ -1104,7 +1105,7 @@ build_timestamp_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "timestamp_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "timestamp_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */
@@ -1248,7 +1249,7 @@ build_pg_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "pg_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "pg_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */
@@ -1529,7 +1530,7 @@ build_ms_prim_gen_query_shader(struct radv_device *device)
* }
* }
*/
nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "ms_prim_gen_query");
nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "ms_prim_gen_query");
b.shader->info.workgroup_size[0] = 64;
/* Create and initialize local variables. */
src/amd/vulkan/radv_shader.c
+2 -1
View File
@@ -13,6 +13,7 @@
#include "nir/nir.h"
#include "nir/nir_builder.h"
#include "nir/nir_xfb_info.h"
#include "nir/radv_meta_nir.h"
#include "nir/radv_nir.h"
#include "spirv/nir_spirv.h"
#include "util/memstream.h"
@@ -3136,7 +3137,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
radv_fill_nir_compiler_options(&options, device, NULL, radv_should_use_wgp_mode(device, stage, &info), dump_shader,
false, false);
nir_builder b = radv_meta_init_shader(device, stage, "meta_trap_handler");
nir_builder b = radv_meta_nir_init_shader(device, stage, "meta_trap_handler");
info.wave_size = 64;
info.workgroup_size = 64;