radeonsi: remove r600_common_context::clear_buffer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-11-25 20:50:31 +01:00
parent b191e2d79d
commit 092756f23f
5 changed files with 4 additions and 20 deletions
@@ -421,16 +421,6 @@ bool si_check_device_reset(struct r600_common_context *rctx)
return true;
}
static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
struct pipe_resource *dst,
uint64_t offset, uint64_t size,
unsigned value)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
}
static bool r600_resource_commit(struct pipe_context *pctx,
struct pipe_resource *resource,
unsigned level, struct pipe_box *box,
@@ -484,7 +474,6 @@ bool si_common_context_init(struct r600_common_context *rctx,
rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
rctx->b.texture_subdata = u_default_texture_subdata;
rctx->b.memory_barrier = r600_memory_barrier;
rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
rctx->b.buffer_subdata = si_buffer_subdata;
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
@@ -595,10 +595,6 @@ struct r600_common_context {
void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value);
void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher);
void (*blit_decompress_depth)(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
-1
View File
@@ -591,5 +591,4 @@ void cik_emit_prefetch_L2(struct si_context *sctx)
void si_init_cp_dma_functions(struct si_context *sctx)
{
sctx->b.b.clear_buffer = si_pipe_clear_buffer;
sctx->b.clear_buffer = si_clear_buffer;
}
+3 -3
View File
@@ -322,9 +322,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
&sctx->null_const_buf);
/* Clear the NULL constant buffer, because loads should return zeros. */
sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0,
R600_COHERENCY_SHADER);
si_clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0,
R600_COHERENCY_SHADER);
}
uint64_t max_threads_per_block;
+1 -1
View File
@@ -292,7 +292,7 @@ void si_test_dma(struct si_screen *sscreen)
set_random_pixels(ctx, src, &src_cpu);
/* clear dst pixels */
sctx->b.clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
si_clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */