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ir3: Assemble and disassemble swz/gat/sct

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
This commit is contained in:
Connor Abbott
2021-04-16 17:13:30 +02:00
committed by Marge Bot
parent d48d43039a
commit 08499369d0
5 changed files with 193 additions and 28 deletions
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src/freedreno/ir3/instr-a3xx.h
+9
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@@ -92,8 +92,17 @@ typedef enum {
/* category 1: */
OPC_MOV = _OPC(1, 0),
OPC_MOVP = _OPC(1, 1),
/* swz, gat, sct */
OPC_MOVMSK = _OPC(1, 3),
/* Virtual opcodes for instructions differentiated via a "sub-opcode" that
* replaces the repeat field:
*/
OPC_SWZ = _OPC(1, 4),
OPC_GAT = _OPC(1, 5),
OPC_SCT = _OPC(1, 6),
/* Logical opcodes for different variants of mov: */
OPC_MOV_IMMED = _OPC(1, 40),
OPC_MOV_CONST = _OPC(1, 41),
src/freedreno/ir3/ir3_lexer.l
+3
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@@ -180,6 +180,9 @@ static int parse_w(const char *str)
"mova" return TOKEN(T_OP_MOVA);
"mov" return TOKEN(T_OP_MOV);
"cov" return TOKEN(T_OP_COV);
"swz" return TOKEN(T_OP_SWZ);
"gat" return TOKEN(T_OP_GAT);
"sct" return TOKEN(T_OP_SCT);
("f16"|"f32"|"u16"|"u32"|"s16"|"s32"|"u8"|"s8"){2} ir3_yylval.str = yytext; return T_CAT1_TYPE_TYPE;
src/freedreno/ir3/ir3_parser.y
+12
View File
@@ -399,6 +399,9 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%token <tok> T_OP_MOVA
%token <tok> T_OP_MOV
%token <tok> T_OP_COV
%token <tok> T_OP_SWZ
%token <tok> T_OP_GAT
%token <tok> T_OP_SCT
/* category 2: */
%token <tok> T_OP_ADD_F
@@ -791,10 +794,19 @@ cat1_mova: T_OP_MOVA T_A0 ',' {
new_reg((61 << 3), IR3_REG_HALF);
} cat1_src
cat1_swz: T_OP_SWZ '.' T_CAT1_TYPE_TYPE { parse_type_type(new_instr(OPC_SWZ), $3); } dst_reg ',' dst_reg ',' src_reg ',' src_reg
cat1_gat: T_OP_GAT '.' T_CAT1_TYPE_TYPE { parse_type_type(new_instr(OPC_GAT), $3); } dst_reg ',' src_reg ',' src_reg ',' src_reg ',' src_reg
cat1_sct: T_OP_SCT '.' T_CAT1_TYPE_TYPE { parse_type_type(new_instr(OPC_SCT), $3); } dst_reg ',' dst_reg ',' dst_reg ',' dst_reg ',' src_reg
/* NOTE: cat1 can also *write* to relative gpr */
cat1_instr: cat1_movmsk
| cat1_mova1
| cat1_mova
| cat1_swz
| cat1_gat
| cat1_sct
| cat1_opc dst_reg ',' cat1_src
| cat1_opc relative_gpr ',' cat1_src
src/freedreno/ir3/tests/disasm.c
+5
View File
@@ -84,6 +84,11 @@ static const struct test {
/* dEQP-VK.subgroups.ballot.compute.compute */
INSTR_6XX(260cc3c0_00000000, "movmsk.w128 r48.x"), /* movmsk.w128 sr48.x */
INSTR_6XX(240cc004_00030201, "swz.u32u32 r1.x, r0.w, r0.y, r0.z"),
INSTR_6XX(2400c105_04030201, "gat.f16u32 r1.y, hr0.y, hr0.z, hr0.w, hr1.x"),
INSTR_6XX(240c0205_04030201, "sct.u32f16 hr1.y, hr0.z, hr0.w, hr1.x, r0.y"),
INSTR_6XX(2400c205_04030201, "sct.f16u32 r1.y, r0.z, r0.w, r1.x, hr0.y"),
INSTR_6XX(20510005_0000ffff, "mov.s16s16 hr1.y, -1"),
INSTR_6XX(20400005_00003900, "mov.f16f16 hr1.y, h(0.625000)"),
INSTR_6XX(20400006_00003800, "mov.f16f16 hr1.z, h(0.500000)"),
src/freedreno/isa/ir3-cat1.xml
+164 -28
View File
@@ -68,14 +68,9 @@ SOFTWARE.
</enum>
<bitset name="#instruction-cat1" extends="#instruction">
<field name="DST" low="32" high="39" type="#cat1-dst">
<param name="DST_REL"/>
</field>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<pattern pos="42">0</pattern>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_REL" pos="49" type="bool"/>
<field name="ROUND" low="55" high="56" type="#round"/>
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
@@ -84,14 +79,40 @@ SOFTWARE.
<map name="SRC">src->regs[1]</map>
<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
<map name="DST_TYPE">src->cat1.dst_type</map>
<map name="DST_REL">!!(src->regs[0]->flags &amp; IR3_REG_RELATIV)</map>
<map name="SRC_TYPE">src->cat1.src_type</map>
<map name="ROUND">src->cat1.round</map>
</encode>
</bitset>
<bitset name="#instruction-cat1-mov" extends="#instruction-cat1">
<bitset name="#instruction-cat1-typed" extends="#instruction-cat1">
<derived name="HALF" type="bool" display="h">
<expr>
({SRC_TYPE} == 0) /* f16 */ ||
({SRC_TYPE} == 2) /* u16 */ ||
({SRC_TYPE} == 4) /* s16 */ ||
({SRC_TYPE} == 6) /* u8 */ ||
({SRC_TYPE} == 7) /* s8 */
</expr>
</derived>
<derived name="DST_HALF" type="bool" display="h">
<expr>
({DST_TYPE} == 0) /* f16 */ ||
({DST_TYPE} == 2) /* u16 */ ||
({DST_TYPE} == 4) /* s16 */ ||
({DST_TYPE} == 6) /* u8 */ ||
({DST_TYPE} == 7) /* s8 */
</expr>
</derived>
<field name="DST_TYPE" low="46" high="48" type="#type"/>
<field name="SRC_TYPE" low="50" high="52" type="#type"/>
<encode>
<map name="DST_TYPE">src->cat1.dst_type</map>
<map name="SRC_TYPE">src->cat1.src_type</map>
</encode>
</bitset>
<bitset name="#instruction-cat1-mov" extends="#instruction-cat1-typed">
<override>
<expr>
({DST} == 0xf4 /* a0.x */) &amp;&amp; ({SRC_TYPE} == 4 /* s16 */) &amp;&amp; ({DST_TYPE} == 4)
@@ -125,27 +146,12 @@ SOFTWARE.
<display>
{SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {ROUND}{DST_HALF}{DST}, {SRC}
</display>
<field name="DST" low="32" high="39" type="#cat1-dst">
<param name="DST_REL"/>
</field>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<field name="DST_REL" pos="49" type="bool"/>
<pattern low="57" high="58">00</pattern> <!-- OPC -->
<derived name="HALF" type="bool" display="h">
<expr>
({SRC_TYPE} == 0) /* f16 */ ||
({SRC_TYPE} == 2) /* u16 */ ||
({SRC_TYPE} == 4) /* s16 */ ||
({SRC_TYPE} == 6) /* u8 */ ||
({SRC_TYPE} == 7) /* s8 */
</expr>
</derived>
<derived name="DST_HALF" type="bool" display="h">
<expr>
({DST_TYPE} == 0) /* f16 */ ||
({DST_TYPE} == 2) /* u16 */ ||
({DST_TYPE} == 4) /* s16 */ ||
({DST_TYPE} == 6) /* u8 */ ||
({DST_TYPE} == 7) /* s8 */
</expr>
</derived>
<field name="DST_TYPE" low="46" high="48" type="#type"/>
<field name="SRC_TYPE" low="50" high="52" type="#type"/>
</bitset>
<!--
@@ -304,6 +310,131 @@ SOFTWARE.
Other newer cat1 instructions
-->
<bitset name="#cat1-multi-src" size="8">
<display>
{HALF}{REG}
</display>
<field name="REG" low="0" high="7" type="#reg-gpr"/>
<encode type="struct ir3_register *">
<map name="REG">src</map>
</encode>
</bitset>
<bitset name="#cat1-multi-dst" size="8">
<display>
{DST_HALF}{REG}
</display>
<field name="REG" low="0" high="7" type="#reg-gpr"/>
<encode type="struct ir3_register *">
<map name="REG">src</map>
</encode>
</bitset>
<bitset name="#instruction-cat1-multi" extends="#instruction-cat1-typed">
<doc>
These instructions all expand to a series of mov instructions,
like (rptN) but more flexible. They aren't any faster than the
equivalent sequence of mov/cov, but they guarantee that all
sources are read before any destination is written, so they
behave as-if the moves are executed in parallel.
TODO: when were these added?
</doc>
<field name="SRC0" low="0" high="7" type="#cat1-multi-src">
<param name="HALF"/>
</field>
<field name="DST0" low="32" high="39" type="#cat1-multi-dst">
<param name="DST_HALF"/>
</field>
<pattern pos="43">0</pattern> <!-- SRC_R -->
<pattern pos="49">0</pattern> <!-- DST_REL -->
<pattern low="53" high="54">00</pattern>
<pattern low="57" high="58">10</pattern> <!-- OPC -->
<encode>
<map name="DST0">src->regs[0]</map>
</encode>
</bitset>
<bitset name="swz" extends="#instruction-cat1-multi">
<doc>
SWiZzle. Move SRC0 to DST0 and SRC1 to DST1 in parallel. In
particular this can be used to swap two registers.
</doc>
<display>
{SY}{SS}{JP}{UL}swz.{SRC_TYPE}{DST_TYPE} {ROUND}{DST0}, {DST1}, {SRC0}, {SRC1}
</display>
<field name="SRC1" low="8" high="15" type="#cat1-multi-src">
<param name="HALF"/>
</field>
<field name="DST1" low="16" high="23" type="#cat1-multi-dst">
<param name="DST_HALF"/>
</field>
<pattern low="24" high="31">00000000</pattern>
<pattern low="40" high="41">00</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[2]</map>
<map name="SRC1">src->regs[3]</map>
<map name="DST1">src->regs[1]</map>
</encode>
</bitset>
<bitset name="gat" extends="#instruction-cat1-multi">
<doc>
GATher. Move SRC0 to DST0, SRC1 to DST0 + 1, SRC2 to DST0 + 2, and SRC3 to DST0 + 3.
</doc>
<display>
{SY}{SS}{JP}{UL}gat.{SRC_TYPE}{DST_TYPE} {ROUND}{DST0}, {SRC0}, {SRC1}, {SRC2}, {SRC3}
</display>
<field name="SRC1" low="8" high="15" type="#cat1-multi-src">
<param name="HALF"/>
</field>
<field name="SRC2" low="16" high="23" type="#cat1-multi-src">
<param name="HALF"/>
</field>
<field name="SRC3" low="24" high="31" type="#cat1-multi-src">
<param name="HALF"/>
</field>
<pattern low="40" high="41">01</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[1]</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC3">src->regs[4]</map>
</encode>
</bitset>
<bitset name="sct" extends="#instruction-cat1-multi">
<doc>
SCaTter. Move SRC0 to DST0, SRC0 + 1 to DST1, SRC0 + 2 to DST2 + 3, and SRC0 + 3 to DST3.
</doc>
<display>
{SY}{SS}{JP}{UL}sct.{SRC_TYPE}{DST_TYPE} {ROUND}{DST0}, {DST1}, {DST2}, {DST3}, {SRC0}
</display>
<field name="DST1" low="8" high="15" type="#cat1-multi-dst">
<param name="DST_HALF"/>
</field>
<field name="DST2" low="16" high="23" type="#cat1-multi-dst">
<param name="DST_HALF"/>
</field>
<field name="DST3" low="24" high="31" type="#cat1-multi-dst">
<param name="DST_HALF"/>
</field>
<pattern low="40" high="41">10</pattern> <!-- SUB_OPC -->
<encode>
<map name="SRC0">src->regs[4]</map>
<map name="DST1">src->regs[1]</map>
<map name="DST2">src->regs[2]</map>
<map name="DST3">src->regs[3]</map>
</encode>
</bitset>
<bitset name="movmsk" extends="#instruction-cat1">
<display>
{SY}{SS}{JP}{UL}movmsk.w{W} {DST}
@@ -314,8 +445,13 @@ SOFTWARE.
</expr>
</derived>
<pattern low="0" high="31">00000000000000000000000000000000</pattern>
<field name="DST" low="32" high="39" type="#cat1-dst">
<param name="DST_REL"/>
</field>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<pattern pos="43">0</pattern> <!-- SRC_R -->
<pattern low="46" high="48">011</pattern> <!-- DST_TYPE==u32 -->
<field name="DST_REL" pos="49" type="bool"/>
<pattern low="50" high="52">011</pattern> <!-- SRC_TYPE==u32 -->
<pattern low="53" high="54">00</pattern>
<pattern low="57" high="58">11</pattern> <!-- OPC -->