nvk: Pass through a shader key for fragment shaders and MSAA
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
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Marge Bot
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a02f65809c
commit
0842cae081
@@ -103,7 +103,8 @@ nvk_compute_pipeline_create(struct nvk_device *device,
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nvk_lower_nir(device, nir, &robustness, pipeline_layout);
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result = nvk_compile_nir(pdevice, nir, &pipeline->base.shaders[MESA_SHADER_COMPUTE]);
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result = nvk_compile_nir(pdevice, nir, NULL,
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&pipeline->base.shaders[MESA_SHADER_COMPUTE]);
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ralloc_free(nir);
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if (result != VK_SUCCESS)
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goto fail;
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@@ -47,6 +47,20 @@ emit_pipeline_rs_state(struct nv_push *p,
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assert(rs->line.mode == VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT);
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}
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static void
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nvk_populate_fs_key(struct nvk_fs_key *key,
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const struct vk_multisample_state *ms)
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{
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memset(key, 0, sizeof(*key));
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if (ms == NULL || ms->rasterization_samples <= 1)
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return;
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key->msaa = ms->rasterization_samples;
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if (ms->sample_shading_enable &&
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(ms->rasterization_samples * ms->min_sample_shading) > 1.0)
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key->force_per_sample = true;
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}
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static void
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emit_pipeline_ms_state(struct nv_push *p,
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const struct vk_multisample_state *ms)
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@@ -172,6 +186,12 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
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pipeline->base.type = NVK_PIPELINE_GRAPHICS;
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struct vk_graphics_pipeline_all_state all;
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struct vk_graphics_pipeline_state state = {};
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result = vk_graphics_pipeline_state_fill(&device->vk, &state, pCreateInfo,
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NULL, &all, NULL, 0, NULL);
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assert(result == VK_SUCCESS);
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for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
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const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i];
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gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
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@@ -194,7 +214,14 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
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nvk_lower_nir(device, nir, &robustness, pipeline_layout);
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result = nvk_compile_nir(pdevice, nir, &pipeline->base.shaders[stage]);
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struct nvk_fs_key fs_key_tmp, *fs_key = NULL;
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if (stage == MESA_SHADER_FRAGMENT) {
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nvk_populate_fs_key(&fs_key_tmp, state.ms);
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fs_key = &fs_key_tmp;
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}
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result = nvk_compile_nir(pdevice, nir, fs_key,
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&pipeline->base.shaders[stage]);
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ralloc_free(nir);
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if (result != VK_SUCCESS)
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goto fail;
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@@ -293,12 +320,6 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
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CONTROL_V_SELECTS_LAYER,
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});
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struct vk_graphics_pipeline_all_state all;
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struct vk_graphics_pipeline_state state = {};
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result = vk_graphics_pipeline_state_fill(&device->vk, &state, pCreateInfo,
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NULL, &all, NULL, 0, NULL);
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assert(result == VK_SUCCESS);
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if (state.ts) emit_pipeline_ts_state(&push, state.ts);
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if (state.vp) emit_pipeline_vp_state(&push, state.vp);
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if (state.rs) emit_pipeline_rs_state(&push, state.rs);
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@@ -640,6 +640,7 @@ nvk_fs_gen_header(struct nvk_shader *fs, struct nv50_ir_prog_info_out *info)
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VkResult
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nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
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const struct nvk_fs_key *fs_key,
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struct nvk_shader *shader)
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{
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struct nv50_ir_prog_info *info;
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@@ -672,6 +673,13 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
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if (ret)
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return VK_ERROR_UNKNOWN;
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if (info_out.bin.fixupData) {
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nv50_ir_apply_fixups(info_out.bin.fixupData, info_out.bin.code,
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fs_key && fs_key->force_per_sample,
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false /* flatshade */, false /* alphatest */,
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fs_key && fs_key->msaa);
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}
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shader->stage = nir->info.stage;
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shader->code_ptr = (uint8_t *)info_out.bin.code;
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shader->code_size = info_out.bin.codeSize;
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@@ -16,6 +16,11 @@ struct nvk_physical_device;
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#define TU102_SHADER_HEADER_SIZE (32 * 4)
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#define NVC0_MAX_SHADER_HEADER_SIZE TU102_SHADER_HEADER_SIZE
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struct nvk_fs_key {
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bool msaa;
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bool force_per_sample;
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};
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struct nvk_shader {
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gl_shader_stage stage;
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@@ -101,6 +106,7 @@ nvk_lower_nir(struct nvk_device *device, nir_shader *nir,
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VkResult
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nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
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const struct nvk_fs_key *fs_key,
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struct nvk_shader *shader);
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VkResult
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