radv: inline gfx10_emit_streamout_{begin,end}()
Instead of having 2 different paths. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19632>
This commit is contained in:
Samuel Pitoiset
committed by
Marge Bot
Marge Bot
parent
09ac29cca9
commit
07dc402a3f
+114
-199
@@ -10521,92 +10521,31 @@ radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
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radeon_emit(cs, 4); /* poll interval */
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}
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static void
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radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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VKAPI_ATTR void VKAPI_CALL
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radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
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struct radv_streamout_state *so = &cmd_buffer->state.streamout;
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struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
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struct radv_shader_info *info = &pipeline->streamout_shader->info;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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radv_flush_vgt_streamout(cmd_buffer);
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assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
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u_foreach_bit(i, so->enabled_mask)
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{
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int32_t counter_buffer_idx = i - firstCounterBuffer;
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if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
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counter_buffer_idx = -1;
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/* AMD GCN binds streamout buffers as shader resources.
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* VGT only counts primitives and tells the shader through
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* SGPRs what to do.
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*/
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radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
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radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
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radeon_emit(cs, info->so.strides[i]); /* VTX_STRIDE (in DW) */
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
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/* The array of counter buffers is optional. */
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RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
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uint64_t va = radv_buffer_get_va(buffer->bo);
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uint64_t counter_buffer_offset = 0;
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if (pCounterBufferOffsets)
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counter_buffer_offset = pCounterBufferOffsets[counter_buffer_idx];
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va += buffer->offset + counter_buffer_offset;
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/* Append */
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, va); /* src address lo */
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radeon_emit(cs, va >> 32); /* src address hi */
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
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} else {
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/* Start from the beginning. */
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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}
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}
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radv_set_streamout_enable(cmd_buffer, true);
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}
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static void
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gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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struct radv_streamout_state *so = &cmd_buffer->state.streamout;
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unsigned last_target = util_last_bit(so->enabled_mask) - 1;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
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assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
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/* Sync because the next streamout operation will overwrite GDS and we
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* have to make sure it's idle.
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* TODO: Improve by tracking if there is a streamout operation in
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* flight.
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*/
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cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
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si_emit_cache_flush(cmd_buffer);
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if (cmd_buffer->device->physical_device->use_ngg_streamout) {
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/* Sync because the next streamout operation will overwrite GDS and we
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* have to make sure it's idle.
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* TODO: Improve by tracking if there is a streamout operation in
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* flight.
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*/
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cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
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si_emit_cache_flush(cmd_buffer);
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} else {
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radv_flush_vgt_streamout(cmd_buffer);
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}
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u_foreach_bit(i, so->enabled_mask)
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{
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@@ -10631,141 +10570,117 @@ gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCou
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
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}
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radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
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radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
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S_411_DST_SEL(V_411_GDS) | S_411_CP_SYNC(i == last_target));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, 4 * i); /* destination in GDS */
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radeon_emit(cs, 0);
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radeon_emit(cs, S_415_BYTE_COUNT_GFX9(4) | S_415_DISABLE_WR_CONFIRM_GFX9(i != last_target));
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if (cmd_buffer->device->physical_device->use_ngg_streamout) {
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radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
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radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) |
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S_411_DST_SEL(V_411_GDS) | S_411_CP_SYNC(i == last_target));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, 4 * i); /* destination in GDS */
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radeon_emit(cs, 0);
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radeon_emit(cs, S_415_BYTE_COUNT_GFX9(4) | S_415_DISABLE_WR_CONFIRM_GFX9(i != last_target));
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} else {
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/* AMD GCN binds streamout buffers as shader resources.
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* VGT only counts primitives and tells the shader through
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* SGPRs what to do.
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*/
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radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
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radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
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radeon_emit(cs, info->so.strides[i]); /* VTX_STRIDE (in DW) */
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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if (append) {
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, va); /* src address lo */
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radeon_emit(cs, va >> 32); /* src address hi */
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} else {
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/* Start from the beginning. */
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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}
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}
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}
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radv_set_streamout_enable(cmd_buffer, true);
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}
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VKAPI_ATTR void VKAPI_CALL
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radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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if (cmd_buffer->device->physical_device->use_ngg_streamout) {
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gfx10_emit_streamout_begin(cmd_buffer, firstCounterBuffer, counterBufferCount,
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pCounterBuffers, pCounterBufferOffsets);
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} else {
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radv_emit_streamout_begin(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,
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pCounterBufferOffsets);
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}
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}
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static void
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radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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struct radv_streamout_state *so = &cmd_buffer->state.streamout;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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radv_flush_vgt_streamout(cmd_buffer);
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assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
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u_foreach_bit(i, so->enabled_mask)
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{
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int32_t counter_buffer_idx = i - firstCounterBuffer;
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if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
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counter_buffer_idx = -1;
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if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
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/* The array of counters buffer is optional. */
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RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
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uint64_t va = radv_buffer_get_va(buffer->bo);
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uint64_t counter_buffer_offset = 0;
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if (pCounterBufferOffsets)
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counter_buffer_offset = pCounterBufferOffsets[counter_buffer_idx];
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va += buffer->offset + counter_buffer_offset;
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
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STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
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radeon_emit(cs, va); /* dst address lo */
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radeon_emit(cs, va >> 32); /* dst address hi */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
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}
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/* Deactivate transform feedback by zeroing the buffer size.
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* The counters (primitives generated, primitives emitted) may
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* be enabled even if there is not buffer bound. This ensures
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* that the primitives-emitted query won't increment.
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*/
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radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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}
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radv_set_streamout_enable(cmd_buffer, false);
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}
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static void
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gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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struct radv_streamout_state *so = &cmd_buffer->state.streamout;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10);
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assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
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u_foreach_bit(i, so->enabled_mask)
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{
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int32_t counter_buffer_idx = i - firstCounterBuffer;
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if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
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counter_buffer_idx = -1;
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if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
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/* The array of counters buffer is optional. */
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RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
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uint64_t va = radv_buffer_get_va(buffer->bo);
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uint64_t counter_buffer_offset = 0;
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if (pCounterBufferOffsets)
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counter_buffer_offset = pCounterBufferOffsets[counter_buffer_idx];
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va += buffer->offset + counter_buffer_offset;
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si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
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radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_PS_DONE, 0,
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EOP_DST_SEL_TC_L2, EOP_DATA_SEL_GDS, va, EOP_DATA_GDS(i, 1), 0);
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
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}
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}
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radv_set_streamout_enable(cmd_buffer, false);
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}
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VKAPI_ATTR void VKAPI_CALL
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radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer,
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uint32_t counterBufferCount, const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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struct radv_streamout_state *so = &cmd_buffer->state.streamout;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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if (cmd_buffer->device->physical_device->use_ngg_streamout) {
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gfx10_emit_streamout_end(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,
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pCounterBufferOffsets);
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} else {
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radv_emit_streamout_end(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,
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pCounterBufferOffsets);
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assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
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if (!cmd_buffer->device->physical_device->use_ngg_streamout)
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radv_flush_vgt_streamout(cmd_buffer);
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u_foreach_bit(i, so->enabled_mask)
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{
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int32_t counter_buffer_idx = i - firstCounterBuffer;
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if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
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counter_buffer_idx = -1;
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bool append =
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counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx];
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uint64_t va = 0;
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if (append) {
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RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
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uint64_t counter_buffer_offset = 0;
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if (pCounterBufferOffsets)
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counter_buffer_offset = pCounterBufferOffsets[counter_buffer_idx];
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va += radv_buffer_get_va(buffer->bo);
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va += buffer->offset + counter_buffer_offset;
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
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}
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if (cmd_buffer->device->physical_device->use_ngg_streamout) {
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if (append) {
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si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
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radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_PS_DONE, 0,
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EOP_DST_SEL_TC_L2, EOP_DATA_SEL_GDS, va, EOP_DATA_GDS(i, 1), 0);
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}
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} else {
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if (append) {
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radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
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radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) | STRMOUT_DATA_TYPE(1) | /* offset in bytes */
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STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
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STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
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radeon_emit(cs, va); /* dst address lo */
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radeon_emit(cs, va >> 32); /* dst address hi */
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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}
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/* Deactivate transform feedback by zeroing the buffer size.
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* The counters (primitives generated, primitives emitted) may
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* be enabled even if there is not buffer bound. This ensures
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* that the primitives-emitted query won't increment.
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*/
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radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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}
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}
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radv_set_streamout_enable(cmd_buffer, false);
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}
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VKAPI_ATTR void VKAPI_CALL
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