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i965/gen9: Set tiled resource mode in surface state

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This patch sets the tiled resource mode for texture and renderbuffer
surfaces.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Anuj Phogat
2015-04-14 22:06:48 -07:00
parent 6b8accb36b
commit 0668756447
2 changed files with 27 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_defines.h
+6
View File
@@ -592,6 +592,12 @@
#define GEN7_SURFACE_MOCS_SHIFT 16
#define GEN7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)
#define GEN9_SURFACE_TRMODE_SHIFT 18
#define GEN9_SURFACE_TRMODE_MASK INTEL_MASK(19, 18)
#define GEN9_SURFACE_TRMODE_NONE 0
#define GEN9_SURFACE_TRMODE_TILEYF 1
#define GEN9_SURFACE_TRMODE_TILEYS 2
/* Surface state DW6 */
#define GEN7_SURFACE_MCS_ENABLE (1 << 0)
#define GEN7_SURFACE_MCS_PITCH_SHIFT 3
src/mesa/drivers/dri/i965/gen8_surface_state.c
+21
View File
@@ -56,6 +56,19 @@ swizzle_to_scs(unsigned swizzle)
return (swizzle + 4) & 7;
}
static uint32_t
surface_tiling_resource_mode(uint32_t tr_mode)
{
switch (tr_mode) {
case INTEL_MIPTREE_TRMODE_YF:
return GEN9_SURFACE_TRMODE_TILEYF;
case INTEL_MIPTREE_TRMODE_YS:
return GEN9_SURFACE_TRMODE_TILEYS;
default:
return GEN9_SURFACE_TRMODE_NONE;
}
}
static uint32_t
surface_tiling_mode(uint32_t tiling)
{
@@ -166,6 +179,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
unsigned tiling_mode, pitch;
const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
if (mt->format == MESA_FORMAT_S_UINT8) {
tiling_mode = GEN8_SURFACE_TILING_W;
@@ -221,6 +235,9 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
(max_level - min_level - 1); /* mip count */
if (brw->gen >= 9)
surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
if (aux_mt) {
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
@@ -351,6 +368,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
unsigned height = mt->logical_height0;
unsigned pitch = mt->pitch;
uint32_t tiling = mt->tiling;
unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
uint32_t format = 0;
uint32_t surf_type;
uint32_t offset;
@@ -440,6 +458,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
surf[5] = irb->mt_level - irb->mt->first_level;
if (brw->gen >= 9)
surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
if (aux_mt) {
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |