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radeonsi/vcn: Fix coded size in sequence header on VCN5

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Introduce coded_width/coded_height for values used in headers
and change it to aligned size on VCN4 to reflect the actual coded size.
VCN5 doesn't have this limitation and can code any size.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
This commit is contained in:
David Rosca
2024-10-04 18:43:17 +02:00
committed by Marge Bot
parent 8b2f0fb574
commit 05f7589fec
3 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+2
View File
@@ -72,6 +72,8 @@ struct radeon_enc_pic {
} hevc;
struct {
struct pipe_av1_enc_picture_desc *desc;
uint32_t coded_width;
uint32_t coded_height;
} av1;
};
src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
+11 -8
View File
@@ -91,6 +91,9 @@ static void radeon_enc_session_init(struct radeon_encoder *enc)
if (!(av1_height % 8) && (av1_height % 16) && !(enc->enc_pic.enable_render_size))
enc->enc_pic.session_init.aligned_picture_height = av1_height + 2;
enc->enc_pic.av1.coded_width = enc->enc_pic.session_init.aligned_picture_width;
enc->enc_pic.av1.coded_height = enc->enc_pic.session_init.aligned_picture_height;
enc->enc_pic.session_init.padding_width =
enc->enc_pic.session_init.aligned_picture_width -
enc->enc_pic.pic_width_in_luma_samples;
@@ -315,16 +318,16 @@ unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_
}
/* frame_width_bits_minus_1 */
width_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
width_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_width);
radeon_enc_code_fixed_bits(enc, width_bits - 1, 4);
/* frame_height_bits_minus_1 */
height_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
height_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height);
radeon_enc_code_fixed_bits(enc, height_bits - 1, 4);
/* max_frame_width_minus_1 */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
width_bits);
/* max_frame_height_minus_1 */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
height_bits);
/* frame_id_numbers_present_flag */
@@ -533,12 +536,12 @@ void radeon_enc_av1_frame_header_common(struct radeon_encoder *enc, bool frame_h
if(frame_size_override) {
/* frame_width_minus_1 */
uint32_t used_bits =
radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_width - 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_width - 1,
radeon_enc_value_bits(enc->enc_pic.av1.coded_width - 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_width - 1,
used_bits);
/* frame_height_minus_1 */
used_bits = radeon_enc_value_bits(enc->enc_pic.session_init.aligned_picture_height - 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.session_init.aligned_picture_height - 1,
used_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height - 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.av1.coded_height - 1,
used_bits);
}
/* render_and_frame_size_different */
src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
+3
View File
@@ -817,6 +817,9 @@ static void radeon_enc_session_init(struct radeon_encoder *enc)
enc->enc_pic.session_init.aligned_picture_height =
align(enc->enc_pic.pic_height_in_luma_samples, 2);
enc->enc_pic.av1.coded_width = enc->enc_pic.pic_width_in_luma_samples;
enc->enc_pic.av1.coded_height = enc->enc_pic.pic_height_in_luma_samples;
enc->enc_pic.session_init.padding_width =
enc->enc_pic.session_init.aligned_picture_width -
enc->enc_pic.pic_width_in_luma_samples;