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i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.

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Shouldn't cause any functional changes at this point, but we have
forgotten to apply this workaround several times in the past, make
sure it doesn't happen again.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
This commit is contained in:
Francisco Jerez
2016-06-30 19:39:24 -07:00
parent 8fd5779da4
commit 04f74d6629
4 changed files with 11 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_misc_state.c
-9
View File
@@ -925,15 +925,6 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
const unsigned dc_flush =
brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
if (brw->gen == 6) {
/* Hardware workaround: SNB B-Spec says:
*
* Before a PIPE_CONTROL with Write Cache Flush Enable = 1, a
* PIPE_CONTROL with any non-zero post-sync-op is required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
src/mesa/drivers/dri/i965/brw_pipe_control.c
+11 -10
View File
@@ -109,6 +109,17 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
OUT_BATCH(0);
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
if (brw->gen == 6 &&
(flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
/* Hardware workaround: SNB B-Spec says:
*
* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
* Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
* required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
BEGIN_BATCH(5);
@@ -325,16 +336,6 @@ brw_emit_mi_flush(struct brw_context *brw)
PIPE_CONTROL_VF_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CS_STALL;
if (brw->gen == 6) {
/* Hardware workaround: SNB B-Spec says:
*
* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
* Flush Enable =1, a PIPE_CONTROL with any non-zero
* post-sync-op is required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
}
brw_emit_pipe_control_flush(brw, flags);
}
src/mesa/drivers/dri/i965/intel_fbo.c
-8
View File
@@ -1061,14 +1061,6 @@ brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
return;
if (brw->gen >= 6) {
if (brw->gen == 6) {
/* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
* Flush Enable = 1, a PIPE_CONTROL with any non-zero
* post-sync-op is required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
src/mesa/drivers/dri/i965/intel_tex.c
-8
View File
@@ -364,14 +364,6 @@ intel_texture_barrier(struct gl_context *ctx)
struct brw_context *brw = brw_context(ctx);
if (brw->gen >= 6) {
if (brw->gen == 6) {
/* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
* Flush Enable = 1, a PIPE_CONTROL with any non-zero
* post-sync-op is required.
*/
brw_emit_post_sync_nonzero_flush(brw);
}
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |